MM74HC161MX ,Synchronous Binary Counter with Asynchronous ClearMM74HC161 • MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Count ..
MM74HC161MX ,Synchronous Binary Counter with Asynchronous ClearGeneral DescriptionWhen the CLEAR is taken LOW the counter is clearedThe MM74HC161 and MM74HC163 sy ..
MM74HC161MX ,Synchronous Binary Counter with Asynchronous ClearGeneral DescriptionWhen the CLEAR is taken LOW the counter is clearedThe MM74HC161 and MM74HC163 sy ..
MM74HC161N ,Synchronous Binary Counter with Asynchronous ClearMM74HC161 • MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Count ..
MM74HC163M ,Synchronous Binary Counter with Synchronous ClearFeaturesoperation will be unaffected.
MM74HC161M-MM74HC161MX-MM74HC161N-MM74HC163M-MM74HC163MX-MM74HC163N
Synchronous Binary Counter with Asynchronous Clear
MM74HC161 • MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Counter with Synchronous Clear September 1983 Revised December 2003 MM74HC161 MM74HC163 Synchronous Binary Counter with Asynchronous Clear Synchronous Binary Counter with Synchronous Clear The MM74HC161 counter is cleared asynchronously. General Description When the CLEAR is taken LOW the counter is cleared The MM74HC161 and MM74HC163 synchronous presetta- immediately regardless of the CLOCK. ble counters utilize advanced silicon-gate CMOS technol- Two active HIGH enable inputs (ENP and ENT) and a RIP- ogy and internal look-ahead carry logic for use in high PLE CARRY (RC) output are provided to enable easy cas- speed counting applications. They offer the high noise cading of counters. Both ENABLE inputs must be HIGH to immunity and low power consumption inherent to CMOS count. The ENT input also enables the RC output. When with speeds similar to low power Schottky TTL. The HC161 enabled, the RC outputs a positive pulse when the counter and the HC163 are 4 bit binary counters. All flip-flops are overflows. This pulse is approximately equal in duration to clocked simultaneously on the LOW-to-HIGH transition the HIGH level portion of the Q output. The RC output is A (positive edge) of the CLOCK input waveform. fed to successive cascaded stages to facilitate easy imple- These counters may be preset using the LOAD input. Pre- mentation of N-bit counters. setting of all four flip-flops is synchronous to the rising edge All inputs are protected from damage due to static dis- of CLOCK. When LOAD is held LOW counting is disabled charge by diodes to V and ground. CC and the data on the A, B, C, and D inputs is loaded into the counter on the rising edge of CLOCK. If the load input is taken HIGH before the positive edge of CLOCK the count Features operation will be unaffected. Typical operating frequency: 40 MHz All of these counters may be cleared by utilizing the Typical propagation delay; clock to Q: 18 ns CLEAR input. The clear function on the MM74HC163 Low quiescent current: 80 μA maximum (74HC Series) counter is synchronous to the clock. That is, the counters are cleared on the positive edge of CLOCK while the clearLow input current: 1 μA maximum input is held LOW.Wide power supply range: 2–6V Ordering Code: Order Number Package Number Package Description MM74HC161M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow (Note 1) MM74HC161SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC161MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide (Note 1) MM74HC161N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HC163M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow (Note 1) MM74HC163SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC163N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2003 DS005008
