MM74HC132MTCX ,Quad 2-Input NAND Schmitt TriggerElectrical Characteristics (Note 4)T = 25°CT = -40 to 85°CT = -40 to 125°CA A AVSymbol Parameter C ..
MM74HC132MTCX ,Quad 2-Input NAND Schmitt TriggerElectrical Characteristics (Note 4)T = 25°CT = -40 to 85°CT = -40 to 125°CA A AVSymbol Parameter C ..
MM74HC132MX ,Quad 2-Input NAND Schmitt TriggerMM74HC132 Quad 2-Input NAND Schmitt TriggerSeptember 1983Revised January 2005MM74HC132Quad 2-Input ..
MM74HC132MX_NL ,Quad 2-Input NAND Schmitt TriggerFeaturesThe MM74HC132 utilizes advanced silicon-gate CMOS
MM74HC132M-MM74HC132MTC-MM74HC132MTCX-MM74HC132MX-MM74HC132MX_NL-MM74HC132N-MM74HC132SJ
Quad 2-Input NAND Schmitt Trigger
MM74HC132 Quad 2-Input NAND Schmitt Trigger September 1983 Revised January 2005 MM74HC132 Quad 2-Input NAND Schmitt Trigger General Description Features The MM74HC132 utilizes advanced silicon-gate CMOSTypical propagation delay: 12 ns technology to achieve the low power dissipation and highWide power supply range: 2V–6V noise immunity of standard CMOS, as well as the capability Low quiescent current: 20 μA maximum (74HC Series) to drive 10 LS-TTL loads. Low input current: 1 μA maximum The 74HC logic family is functionally and pinout compatible Fanout of 10 LS-TTL loads with the standard 74LS logic family. All inputs are protected Typical hysteresis voltage: 0.9V at V =4.5V from damage due to static discharge by internal diode CC clamps to V and ground. CC Ordering Code: Package Order Number Package Description Number MM74HC132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC132MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC132SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC132N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.) Pb-Free package per JEDEC J-STD-020B. Connection Diagram Logic Diagram Pin Assignment for DIP, SOIC, SOP, and TSSOP Top View © 2005 DS005309
