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MM74HC08SJX , Quad 2-Input AND Gate
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MN4001B ,Microcomputers Application-Specific Standard-Product ICsMaintenance/DiscontinuedMaintenance/Discontinued includes following four Product lifecycle stage.pl ..
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MM74HC08M-MM74HC08MTC-MM74HC08MTCX-MM74HC08MX-MM74HC08N
Quad 2-Input AND Gate
MM74HC08 Quad 2-Input AND Gate September 1983 Revised January 2005 MM74HC08 Quad 2-Input AND Gate General Description Features The MM74HC08 AND gates utilize advanced silicon-gateTypical propagation delay: 7 ns (t ), 12 ns (t ) PHL PLH CMOS technology to achieve operating speeds similar to Fanout of 10 LS-TTL loads LS-TTL gates with the low power consumption of standard Quiescent power consumption: 2 μA maximum at room CMOS integrated circuits. The HC08 has buffered outputs, temperature providing high noise immunity and the ability to drive 10 Low input current: 1 μA maximum LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static dis- charge by internal diode clamps to V and ground. CC Ordering Code: Package Order Number Package Description Number MM74HC08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC08MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC08SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC08MTCX-NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC08N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A) Pb-Free package per JEDEC J-STD-020B. Connection Diagram Top View © 2005 DS005297