MM74HC04MTCX ,Hex InverterFeaturesThe MM74HC04 inverters utilize advanced silicon-gate
MM74HC04M-MM74HC04MTCX-MM74HC04MX-MM74HC04MX_NL-MM74HC04N-MM74HC04SJ-MM74HC04SJX
Hex Inverter
MM74HC04 Hex Inverter September 1983 Revised January 2005 MM74HC04 Hex Inverter General Description Features The MM74HC04 inverters utilize advanced silicon-gateTypical propagation delay: 8 ns CMOS technology to achieve operating speeds similar toFan out of 10 LS-TTL loads LS-TTL gates with the low power consumption of standard Quiescent power consumption: 10 μW maximum at CMOS integrated circuits. room temperature The MM74HC04 is a triple buffered inverter. It has high Low input current: 1 μA maximum noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by inter- nal diode clamps to V and ground. CC Ordering Code: Package Order Number Package Description Number MM74HC04M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC04M_NL Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC04SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC04MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC04MTC_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC04N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HC04N_NL N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Logic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP 1 of 6 Inverters Top View © 2005 DS005069
