MM74HC02MX ,Quad 2-Input NOR GateMM74HC02 Quad 2-Input NOR GateSeptember 1983Revised January 2005MM74HC02Quad 2-Input NOR Gate
MM74HC02N ,Quad 2-Input NOR GateMM74HC02 Quad 2-Input NOR GateSeptember 1983Revised January 2005MM74HC02Quad 2-Input NOR Gate
MM74HC04M ,Hex InverterMM74HC04 Hex InverterSeptember 1983Revised January 2005MM74HC04Hex Inverter
MM74HC04MTCX ,Hex InverterElectrical Characteristics (Note 4)T = 25°CT = −40 to 85°CT = −55 to 125°CA A A Symbol Parameter C ..
MM74HC04MTCX ,Hex InverterFeaturesThe MM74HC04 inverters utilize advanced silicon-gate
MM74HC02M-MM74HC02MTC-MM74HC02MX-MM74HC02N
Quad 2-Input NOR Gate
MM74HC02 Quad 2-Input NOR Gate September 1983 Revised January 2005 MM74HC02 Quad 2-Input NOR Gate General Description Features The MM74HC02 NOR gates utilize advanced silicon-gateTypical propagation delay: 8 ns CMOS technology to achieve operating speeds similar toWide power supply range: 2–6V LS-TTL gates with the low power consumption of standard Low quiescent supply current: 20 μA maximum CMOS integrated circuits. All gates have buffered outputs, (74HC Series) providing high noise immunity and the ability to drive 10 Low input current: 1 μA maximum LS-TTL loads. The 74HC logic family is functionally as well High output current: 4 mA minimum as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static dis- charge by internal diode clamps to V and ground. CC Ordering Code: Package Order Number Package Description Number MM74HC02M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC02SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC02MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC02MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC02N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A.) Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Assignment for DIP, SOIC, SOP and TSSOP Top View Logic Diagram © 2005 DS005294
