MM74HC00MTCX ,Quad 2-Input NAND GateMM74HC00 Quad 2-Input NAND GateSeptember 1983Revised January 2005MM74HC00Quad 2-Input NAND Gate
MM74HC00MX ,Quad 2-Input NAND GateFeaturesThe MM74HC00 NAND gates utilize advanced silicon-gate
MM74HC00M-MM74HC00MTC-MM74HC00MTCX-MM74HC00MX-MM74HC00N-MM74HC00SJ-MM74HC00SJX
Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate September 1983 Revised January 2005 MM74HC00 Quad 2-Input NAND Gate General Description Features The MM74HC00 NAND gates utilize advanced silicon-gateTypical propagation delay: 8 ns CMOS technology to achieve operating speeds similar toWide power supply range: 2–6V LS-TTL gates with the low power consumption of standard Low quiescent current: 20 μA maximum (74HC Series) CMOS integrated circuits. All gates have buffered outputs. Low input current: 1 μA maximum All devices have high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is function-Fanout of 10 LS-TTL loads ally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V and CC ground. Ordering Code: Package Order Number Package Description Number MM74HC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC00MX_NL M14A Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74HC00SJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC00MTCX_NL MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HC00N_NL N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Logic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © 2005 DS005292
