MM74C73N ,Dual J-K Flip-Flops with Clear and PresetApplications• Automotive Data terminals Instrumentation Medical electronics Alarm systems Indu ..
MM74C74M ,Dual D Flip-FlopMM74C74 Dual D-Type Flip-FlopOctober 1987Revised May 2002MM74C74Dual D-Type Flip-Flop
MM74C74N ,Dual D Flip-FlopFeaturesThe MM74C74 dual D-type flip-flop is a monolithic comple-
MM74C73N
Dual J-K Flip-Flops with Clear and Preset
MM74C73 Dual J-K Flip-Flops with Clear and Preset October 1987 Revised January 2004 MM74C73 Dual J-K Flip-Flops with Clear and Preset General Description Features The MM74C73 dual J-K flip-flops are monolithic comple-Supply voltage range: 3V to 15V mentary MOS (CMOS) integrated circuits constructed withTenth power TTL compatible: Drive 2 LPTTL loads N- and P-channel enhancement transistors. Each flip-flop High noise immunity: 0.45 V (typ.) CC has independent J, K, clock and clear inputs and Q and Q Low power: 50 nW (typ.) outputs. This flip-flop is edge sensitive to the clock input and change state on the negative going transition of theMedium speed operation: 10 MHz (typ.) clock pulse. Clear or preset is independent of the clock and is accomplished by a low level on the respective input. Applications • Automotive Data terminals Instrumentation Medical electronics Alarm systems Industrial electronics Remote metering Computers Ordering Code: Order Number Package Number Package Description MM74C73N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Truth Table t t n n+1 JK Q 00 Q n 010 101 11 Q n Q Q Preset Clear n n 0000 0110 1001 11 Q Q n n (Note 1) (Note 1) Note: A logic “0” on clear sets Q to logic “0”. t = bit time before clock pulse n t = bit time after clock pulse Top View n+1 Note 1: No change in output from previous state © 2004 DS005884
