MM74C48N ,BCD-to-7 Segment DecoderFeaturesThe MM74C48 BCD-to-7 segment decoder is a monolithic
MM74C48N
BCD-to-7 Segment Decoder
MM74C48 BCD-to-7 Segment Decoder October 1987 Revised May 2002 MM74C48 BCD-to-7 Segment Decoder General Description Features The MM74C48 BCD-to-7 segment decoder is a monolithicWide supply voltage range: 3.0V to 15V complementary MOS (CMOS) integrated circuit con-Guaranteed noise margin: 1.0V structed with N- and P-channel enhancement transistors. High noise immunity: 0.45 V (typ.) CC Seven NAND gates and one driver are connected in pairs Low power TTL compatibility: to make binary-coded decimal (BCD) data and its comple- ment available to the seven decoding AND-OR-INVERT fan out of 2 driving 74L gates. The remaining NAND gate and three input buffers High current sourcing output (up to 50 mA) provide test-blanking input/ripple-blanking output, and rip- Ripple blanking for leading or trailing zeros (optional) ple-blanking inputs. Lamp test provision Ordering Code: Order Number Package Number Package Description MM74C48N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagrams Segment Identification Numerical Designations and Resultant Displays Top View © 2002 DS005883
