MM74C175N ,Quad D-Type Flip-FlopFeaturesThe MM74C175 consists of four positive-edge triggered D-
MM74C175N
Quad D-Type Flip-Flop
MM74C175 Quad D-Type Flip-Flop October 1987 Revised January 2004 MM74C175 Quad D-Type Flip-Flop General Description Features The MM74C175 consists of four positive-edge triggered D-Wide supply voltage range: 3V to 15V type flip-flops implemented with monolithic CMOS technol-Guaranteed noise margin: 1.0V ogy. Both are true and complemented outputs from each High noise immunity: 0.45 V (typ.) CC flip-flop are externally available. All four flip-flops are con- Low power TTL compatibility: Fan out of 2 driving 74L trolled by a common clock and a common clear. Informa- tion at the D-type inputs meeting the set-up time requirements is transferred to the Q outputs on the posi- tive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all four Q outputs to logical “0” and Q's to logical “1”. All inputs are protected from static discharge by diode clamps to V and GND. CC Ordering Code: Order Number Package Number Package Description MM74C175N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Truth Table Each Flip-Flop Inputs Outputs Clear Clock D Q Q LX X L H H ↑ HH L H ↑ LL H HH X NC NC HL X NC NC H = HIGH Level L = LOW Level X = Irrelevant ↑ = Transition from LOW-to-HIGH level NC = No Change Top View © 2004 DS005900
