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MK50H27 ,SIGNALLING SYSTEM 7 LINK CONTROLLERFEATURESComplete Level 2 Implementation of SS7.Compatible with 1988 CCITT, AT&T, ANSI,and Bellcore ..
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MK50H27
SIGNALLING SYSTEM 7 LINK CONTROLLER
MK50H27
Signalling System 7
Link Controller
SECTION 1 - FEATURES
Complete Level 2 Implementation of SS7.
Compatible with 1988 CCITT, AT&T, ANSI,
and Bellcore Signalling System Number 7 link
level protocols.
Optional operation to comply with Japanese
TTC JT-Q703 specification requirements
Pin-for-pin and architecturally compatible with
MK50H25 (X.25/LAPD), MK50H29 (SDLC),
and MK50H28(Frame Relay).
System clock rates up to 33 MHz (MK50H27 -
33), or 25 MHz (MK50H27 - 25).
Data rate up to 4 Mbps continuous for SS7
protocol processing, 20 Mbps for transparent
HDLC mode, or up to 51 Mbps bursted
(gapped data clocks, non-continuous data).
On chip DMA control with programmable burst
length.
DMA transfer rate of up to 13.3 Mbytes/sec us-
ing optional 5 SYSCLK DMA cycle (150 nS) at
33 MHz SYSCLK.
Buffer Management includes:
- Initialization Block
- Separate Receive and Transmit Rings
- Variable Descriptor Ring and Window Sizes.
Selectable BEC or PCR retransmission meth-
ods, including forced retransmission for PCR.
Handles all 7 SS7 Timers, plus the additional
Signal Unit interval timers for Japanese SS7.
Handles all SS7 frame formatting:
- Zero bit insert and delete
- FCS generation and detection
- Frame delimiting with flags
Programmable minimum Signal Unit spacing
(number of flags between SU’s)
Handles all sequencing and link control.
Selectable FCS of 16 or 32 bits.
Testing Facilities:
- Internal Loopback
- Silent Loopback
- Optional Internal Data Clock Generation
- Self Test.
Programmable for full or half duplex operation
Programmable Watchdog Timers for RCLK
and TCLK (to detect absence of data clocks)
Available in 52 pin PLCC, 84 pin PLCC(for use
with external ROM), or 48 pin DIP packages.
SECTION 2 - INTRODUCTION
The SGS - Thomson SS7 Signalling Link Control-
ler (MK50H27) is a VLSI semiconductor device
which provides a complete level 2 data communi-
cation control conforming to the CCITT, ANSI,
BELLCORE, and AT&T versions of SS7, as well
as options to allow conformance to TTC JT-Q703
(Japanese SS7). This includes signal unit format-
ting, transparency (so-called "bit-stuffing"), error
recovery by two types of retransmission, error
monitoring, sequence number control, link status
control, and fill in signal unit generation.
One of the outstanding features of the MK50H27
is its buffer management which includes on-chip
DMA. This feature allows users to handle multi-
ple MSU’s of receive and transmit data at a time.
(A conventional data link control chip plus a sepa-
rate DMA chip would handle data for only a single
block at a time.) The MK50H27 will move multiple
blocks of receive and transmit data directly into
INTRODUCTION (Continued)
and out of memory through the Host’s bus. A
possible system configuration for the MK50H27 is
shown in figure 1.
For added flexibility a transparent mode provides
an HDLC transport mechanism without link layer
support. In this mode no protocol processing is
done, all data received between opening flag and
CRC is written to the shared memory buffer and it
is up to the user to take care of the upper level
software.
The MK50H27 may be used with any of several
popular microprocessors, such as: 68040 ...
68000, 6800, Z8000, Z80, 80486 ... 8086, i960,
etc.
The MK50H27 may be operated in either full or
half duplex mode. In half duplex mode, the RTS
and CTS modem control pins are provided. In full
duplex mode, these pins become user program-
mable I/O pins. All signal pins on the MK50H27
are TTL compatible. This has the advantage of
making the MK50H27 independent of the physical
interface. As shown in figure 1, line drivers and
receivers are used for electrical connection to the
physical layer.
DIP48 PIN CONNECTION (Top view)
2/56
PLCC52 PIN CONNECTION (Top view)
TAble 1 - PIN DESCRIPTION
LEGEND:
I Input only O Output only
IO Input / Output 3S 3-State
OD Open Drain (no internal pull-up)
Note: Pin out for 52 pin PLCC is shown in brackets.
4/56
Table 1: PIN DESCRIPTION (continued)
Table 1: PIN DESCRIPTION (continued)
SECTION 3
OPERATIONAL DESCRIPTION
The SGS-Thomson MK50H27 Multi-Logical Link
Communications Controller device is a VLSI prod-
uct intended for high performance data communi-
cation applications requiring SDLC link level con-
trol. The MK50H27 will perform all frame
formatting, such as: frame delimiting with flags,
FCS (CRC) generation and detection, and zero
bit insertion and deletion for transparency. The
MK50H27 also handles all supervisory (S) and
unnumbered (U) frames (see Tables A & B). The
MK50H27 also includes a buffer management
mechanism that allows the user to transmit and/or
receive multiple frames for each active channel
or DLCI. Contained in the buffer management is
an on-chip dual channel DMA: one channel for re-
ceive and one channel for transmit.
The MK50H27 can be used with any popular 16
or 8 bit microprocessor. A possible system con-
figuration for the MK50H27 is shown in Figure 1.
This document assumes that the processor has a
byte addressable memory organization.
The MK50H27 will move multiple blocks of re-
ceive and transmit data directly in and out of
memory through the Host’s bus.
The MK50H27 may be operated in full or half du-
plex mode. In half duplex mode the RTS and
CTS modem control pins are provided. In full du-
plex mode, these pins become user programma-
ble I/O pins.
All signal pins on the MK50H27 are TTL compat-
ible. This has the advantage of making the
MK50H27 independent of the physical interface.
As shown in Fig. 1, line drivers and receivers are
used for electrical connection to the physical
layer.
6/56
Figure 1: Possible System Configuration for thr MK50H27
Figure 2: MK50H27 Simplified Block Diagram
8/56
3.1 Functional Blocks
Refer to the block diagram in Figure 2.
The MK50H27 is primarily initialized and control-
led through six 16-bit Control and Status Regis-
ters (CSR0 thru CSR5). The CSR’s are accessed
through two bus addressable ports, the Register
Address Port (RAP), and the Register Data Port
(RDP). The MK50H27 may also generate an in-
terrupt(s) to the Host. These interrupts are en-
abled and disabled through CSR0.
The on-chip microcontroller is used to control the
movement of parallel receive and transmit data,
and to handle the Address field filtering.
3.1.1 Microcontroller
The microcontroller controls all of the other blocks
of the MK50H27. The microcontroller performs
frame processing and protocol processing. All
primitive processing and generation is also done
here. The microcode ROM contains the control
program of the microcontroller.
3.1.2 Receiver
Serial receive data comes into the Receiver (Fig-
ure 2). The Receiver is responsible for:
1. Leading and trailing flag detection.
2. Deletion of zeroes inserted for transparency.
3. Detection of idle and abort sequences.
4. Detection of good & bad CK (ChecK bit seq.)
5. Monitoring Receiver FIFO status.
6. Detection of Receiver Over-Run.
7. Odd byte detection.
NOTE: If frames are received that have an odd
number of bytes then the last byte of the
frame is said to be an odd byte.
8. Detection of non-octet aligned frames. Such
frames are treated as invalid.
3.1.3 Transmitter
The Transmitter is responsible for:
1. Serialization of outgoing data.
2. Generating and appending the CK (CRC).
3. Framing outgoing frame with flags.
4. Zero bit insertion for transparency.
5. Transmitter Under-Run detection.
6. Transmission of odd byte.
7. RTS/CTS control.
3.1.4 Check Bit Sequence or Cyclic
The CK (CRC) on the transmitter or receiver may
be either 16 bit or 32 bit, and is user selectable.
For full duplex operation, both the receiver and
transmitter have individual CK computation cir-
cuits. The characteristics of the CK are:
Transmitted Polarity: Inverted
Transmitted Order: High Order Bit First
Pre-set Value: All 1’s
Polynomial 16 bit: 16 + X12 + X5 + 1
Remainder 16 bit (if received correctly):
High order bit-->0001 1101 0000 1111
Polynomial 32 bit: 32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 +8 + X7 + X5 + X4 + X2 + X + 1
Remainder 32 bit (if received correctly):
high order bit-->1100 0111 0000 0100
1101 1101 0111 1011
3.1.5 Receive FIFO
The Receive FIFO buffers the data received by
the receiver. This performs two major functions.
First, it resynchronizes the data from the receive
clock to the system clock. Second, it allows the
microcontroller time to finish whatever it may be
doing before it has to process the received data.
The receive FIFO holds the data from the receiver
without interrupting the microcontroller for service
until it contains enough data to reach the water-
mark level, or an end of frame is received. This
watermark level can be programmed in CSR4
(FWM) to occur when the FIFO contains at least
18 or more bytes; 34 or more bytes; or 50 or
more bytes. This programmability , along with the
programmable burst length of the DMA controller,
enables the user to define how often and for how
long the MK50H27 must use the host bus. For
more information, see CSR4.
For example, if the watermark level is set at 34
bytes and the burst length is limited to 8 word
transfers at a time, the MK50H27 will request
control of the host bus as soon as 34 bytes are
received and again after every 16 subsequent
bytes.
3.1.6 Transmit FIFO
The Transmit FIFO buffers the data to be trans-
mitted by the MK50H27. This also performs two
major functions. First, it resynchronizes the data
from the system clock to the transmit clock. Sec-
ond, it allows the microcontroller and DMA con-
troller to burst read data from the host’s memory
buffers; making both the MK50H27 and the host
bus more efficient.
The transmit FIFO has a watermark scheme simi-
lar to the one described for the receive FIFO
above, and uses the same FWM value selections
in CSR4 for the watermark. Once filled to within
FWM of being full (by DMA from TX buffer in
shared memory), the transmit FIFO will not inter-
rupt the microcontroller until it empties enough to
fall below the watermark level.
3.1.7 DMA Controller
The MK50H27 has an on-chip DMA Controller cir-
cuit. This allows it to access memory without re-
quiring host software intervention. Whenever the
MK50H27 requires access to the host memory it
will negotiate for mastership of the bus. Upon
gaining control of the bus the MK50H27 will begin
transferring data to or from memory. The
MK50H27 will perform memory transfers until
either it has nothing more to transfer, it has
reached its DMA burst limit (user programmable),
or the BUSREL pin is driven low. In any case, it
will complete all bus transfers before releasing
bus mastership back to the host. If during a
memory transfer, the memory does not respond
within 256 SCLK cycles, the MK50H27 will re-
lease ownership of the bus immediately and the
MERR bit will be set in CSR0. The DMA burst
limit can be programmed by the user through
CSR4. In 16 bit mode the limit can be set to 1
word, 8 words, or unlimited word transfers. In 8
bit mode,it can be set to 2 bytes, 16 bytes, or un-
limited byte transfers. For high speed data lines
(i.e. > 1 Mbps) a burst limit of 8 words or 16 bytes
is suggested to allow maximum throughput.
The byte ordering of the DMA transfers can be
programmed to account for differences in proces-
sor architectures or host programming languages.
Byte ordering can be programmed separately for
data and control information. Data information is
defined as all contents of data buffers; control in-
formation is defined as anything else in the
shared memory space (i.e. initialization block, de-
scriptors, etc). For more information see section
4.1.2.5 on control status register 4.
3.1.8 Bus Slave Circuitry
The MK50H27 contains a bank of internal con-
trol/status registers (CSR0-5) which can be ac-
cessed by the host as a peripheral. The host can
read or write to these registers like any other bus
slave. The contents of these registers are listed
in Section 4 and bus signal timing is described in
Figures 9 and 10.
3.2 Buffer Management Overview
Refer to Fig. 3.
3.2.1 Initalization Block
Chip initialization information is located in a block
of memory called the Initialization Block. The In-
itialization Block consists of 200 contiguous words
of memory starting on a word boundary. This
memory is assembled by the HOST, and is ac-
cessed by the MK50H27 during initialization. The
Initialization Block is comprised of:
A. Mode of Operation.
B. Counter/Timer Preset Values.
C. Protocol Parameters or Options
D. Location and size of Receive and Transmit De-
scriptor Rings.
E. Optional Transmit Window SIze Value
F. Location of Status Buffer.
G. Optional JT-Q703 Signal Unit Interval Timer
Values
H. Statistics and Error Counters.
3.2.2 The Circular Queue
The basic organization of the buffer management
is a circular queue of tasks in memory called de-
scriptor rings. There are separate rings to de-
scribe the transmit and receive operations. Up to
128 buffers may be queued-up on a descriptor
ring awaiting execution by the MK50H27. The
descriptor ring has a descriptor assigned to each
buffer. Each descriptor holds a pointer for the
starting address of the buffer, and holds a value
for the length of the buffer in bytes.
Each descriptor also contains two control bits
called OWNA and OWNB, which denote whether
the MK50H27, the HOST, or an I/O ACCELERA-
TION PROCESSOR ( if present ) "owns" the buff-
er. For transmit, when the MK50H27 owns the
buffer, the MK50H27 is allowed and commanded
to transmit the buffer. When the MK50H27 does
not own the buffer, it will not transmit that buffer.
For receive, when the MK50H27 owns a buffer, it
may place received data into that buffer. Con-
versely, when the MK50H27 does not own a re-
ceive buffer, it will not place received data into
that buffer.
The MK50H27 buffer management mechanism
will handle frames which are longer than the
length of an individual buffer. This is done by a
chaining method which utilizes multiple buffers.
The MK50H27 tests the next descriptor in the de-
scriptor ring in a "look ahead" manner. If the
frame is too long for one buffer, the next buffer
will be used after filling the first buffer; that is,
"chained". The MK50H27 will then "look ahead"
to the next buffer, and chain that buffer if neces-
sary, and so on.The operational parameters for
the buffer management are defined by the user in
the initialization block. The parameters defined
include the basic mode of operation, protocol op-
tions, the number of entries for the transmitter
10/56
and receiver descriptor rings, etc. The starting
address for the Initialization block, IADR, is de-
fined in the CSR2 and CSR3 registers inside the
MK50H27.
3.2.3 Signal Unit Repertoire
The frame format
shown in Table
consist of a programmable number of leading flag
patterns (01111110),
ber, Backward
Number,
Field, followed by Signalling Information
Service Information
pending on SU type, and
(CRC) of either 16
pattern. The number of leading flags transmitted
is programmable
the Initialization Block. Received signal units may
have as few as one flag between adjacent signal
units
The symbols and definitions for the signal unit
types handled by the MK50H27 are:
TABLE A - MK50H27 Signal Unit Repertoire
Message Signal Unit (MSU)
Link Status Signal Unit (LSSU) 16/32 8n,n>=2 8 2 6 1 7 1 7 8 16/32 17 1 7 88/16
Values for SF:
0 - SIO,
1 - SIN,
2 - SIE,
Out of alignment
Normal alignment
Emergency 6 171 7 8
Fill-in Signal Unit (FISU) 16/32
Right-most fields are transmitted first
3 - SIOS,
4 - SIPO,
5 - SIB,
Out-of-service
Processor outage
Congestion (Busy)
TABLE A - MK50H27 Signal Unit Repertoire
12/56
Figure 3: MK50H27 Memory Management Structure
SECTION 4
PROGRAMMING SPECIFICATION
This section defines the Control and Status Reg-
isters and the memory data structures required to
program the MK50H27.
4.1 Control and Status Registers
There are six Control and Status Registers
(CSR’s) resident within the MK50H27. The
CSR’s are accessed through two bus address-
able ports, an address port (RAP), and a data
port (RDP), thus requiring only two locations in
the system memory or I/O map.
4.1.1 Accessing the Control & Status Registers
The CSR’s are read (or written) in a two step op-
eration. The address of the CSR is written into the
address port (RAP) during a bus slave transac-
tion. During a subsequent bus slave transaction,
the data being read from (or written into) the data
port (RDP) is read from (or written into) the CSR
selected in the RAP. Once written, the address in
RAP remains unchanged until rewritten or upon a
bus reset. A control I/O pin (ADR) is provided to
distinguish the address port from the data port.
ADR Port
L Register Data Port (RDP)
H Register Address Port (RAP)
4.1.1.1 Register Address Port (RAP)
14/56
4.1.1.2 Register Data Port (RDP)
4.1.2 Control and Status Register Definition
4.1.2.1 Control and Status Register 0 (CSR0)
RAP<3:1> = 0
BIT NAME DESCRIPTION
15 TDMD TRANSMIT DEMAND, when set, causes MK50H27 to access the
Transmit Descriptor Ring without waiting for the transmit polltime inter-
val to elapse. TDMD need not be set to transmit a MSU, it merely has-
tens MK50H27’s response to a Transmit Descriptor Ring entry inser-
tion by the host. TDMD is Write With ONE ONLY and cleared by the
microcode after it is used. It may read as a "1" for a short time after it
is written because the microcode may have been busy when TDMD
was set. It is also cleared by Bus RESET. Writing a "0" in this bit has
no effect.
14 POFF POFF, when set, indicates that MK50H27 is operating in the Power Off
phase of operation. All external activity is disabled and internal logic is
reset. MK50H27 remains inactive except for primitive processing until
a Power On primitive is issued. POFF IS READ ONLY and set by Bus
RESET or a Power Off primitive. Writing to this bit has no effect.
13 DTX Transmitter ring disable prevents the MK50H27 from further access to
the Transmitter Descriptor Ring and terminates transmitter polling. No
transmissions are attempted after finishing transmission of any signal
unit in transmission at the time of DTX being set. TXON acknow-
ledges changes to DTX, see below. DTX is READ/WRITE.
4.1.2.1 Control and Status Register 0 (CSR0)
BIT
12 DRX Disable the Receiver prevents the MK50H27 from further access to
the Receiver Descriptor Ring. No received signal units are accepted
after finishing reception of any signal unit in reception at the time
of DRX being set. RXON acknowledges changes to DRX, see be-
low. DRX is READ/WRITE.
11 TXON TRANSMITTER ON indicates that the transmit ring access is enabled.
TXON is set as the Power On primitive is issued if the DTX bit is "0"
or afterward as DTX is cleared. TXON is cleared upon recognition of
DTX being set, by sending a Power Off primitive in CSR1, or by a
Bus RESET. If TXON is clear, the host may modify the Transmit
Descriptor Ring entries regardless of the state of the OWNA bits.
TXON is READ ONLY; writing to this bit has no effect.
10 RXON RECEIVER ON indicates that the receive ring access is enabled.
RXON is set as the Power On primitive is issued if DRX=0, or after-
ward as DRX is cleared. RXON is cleared upon recognition of DRX
being set, by sending a Power Off primitive in CSR1, or by a
Bus RESET. RXON is READ ONLY; writing to this bit has no effect.
09 INEA INTERRUPT ENABLE allows the INTR I/O pin to be driven low when
the Interrupt Flag is set. If INEA = 1 and INTR = 1 the INTR I/O pin will
be low. If INEA = 0 the INTR I/O pin will be high, regardless of the
state of the Interrupt Flag. INEA is READ/WRITE set by writing a
"1" into this bit and is cleared by writing a "0" into this bit, by Bus RE-
SET, or while in the Power Off phase. INEA may not be set while in
the Power Off phase.
08 INTR INTERRUPT FLAG indicates that one or more of the following interrupt
causing conditions has occurred: MISS, MERR, RINT, TINT, PINT. If
INEA = 1 and INTR = 1 the INTR I/O pin will be low. INTR is READ
ONLY, writing this bit has no effect. INTR is cleared as the specific
interrupting condition bits are cleared. INTR is also cleared by Bus
RESET or by issuing a Power Off primitive.
07 MERR MEMORY ERROR is set when the MK50H27 is the Bus Master and
READY has not been asserted within 256 SYSCLKs (25.6 usec @
10MHz) after asserting the address on theDAL lines. When a Mem-
ory Error is detected, the MK50H27 releases the bus, the receiver
and transmitter are turned off, and an interrupt is generated if INEA =
1. MERR is READ/CLEAR ONLY and is set by the chip and cleared by
writing a "1" into the bit. Writing a "0" has no effect. It is cleared by
Bus RESET or by issuing a Power Off primitive.
06 MISS MISSED MSU is set when the receiver loses a MSU because it does
not own a receive buffer indicating loss of data. When MISS is set, an
interrupt will be generated if INEA = 1. MISS is READ/CLEAR ONLY
and is set by MK50H27 and cleared by writing a "1" into the bit. Writ-
ing a "0" has no effect. It is also cleared by Bus RESET or by issu-
ing a Power Off primitive.
05 ROR RECEIVER OVERRUN indicates that the Receiver FIFO was full When
the receiver was ready to input data to the Receiver FIFO. The sig-
nal unit being received is lost but is recoverable according to the Link
Level protocol. When ROR is set, an interrupt is generated if INEA =
1. ROR is READ/CLEAR ONLY and is set by MK50H27 and cleared
by writing a "1" into the bit. Writing a "0" has no effect. It is also
cleared by Bus RESET or by issuing a Power Off primitive.
16/56
04 TUR TRANSMITTER UNDERRUN indicates that the MK50H27 has aborted
a signal unit since data was late from memory. This condition is
reached when the transmitter and transmitter FIFO both become
empty while transmitting a signal unit. When TUR is set, an interrupt
is generated if INEA = 1. TUR is READ/CLEAR ONLY and is set by
MK50H27 and cleared by writing a "1" into the bit. Writing a "0" has
no effect. It is also cleared by RESET or by issuing a Power Off primi-
tive.
03 PINT PRIMITIVE INTERRUPT is set after the chip updates the primitive
register to issue a provider primitive. When PINT is set, an interrupt is
generated if INEA =1. PINT is READ/CLEAR ONLY and is set by
MK50H27 and cleared by writing a "1" into the bit. Writing a "0" has no
effect. It is also cleared by RESET or by issuing a Power Off primitive.
02 TINT TRANSMITTER INTERRUPT is set after the chip updates an entry
in the Transmit Descriptor Ring. When TINT is set, an interrupt is
generated if INEA =1. TINT is READ/CLEAR ONLY and is set by
MK50H27 and cleared by writing a "1" into the bit. Writing a "0" has no
effect. It is also cleared by RESET or by issuing a PowerOff primitive. RINT RECEIVER INTERRUPT is set after the MK50H27 updates an entry in
the Receive Descriptor Ring. When RINT is set, an interrupt is gener-
ated if INEA =1. RINT is READ/CLEAR ONLY and is set by MK50H27
and cleared by writing a "1" into the bit. Writing a "0" has no effect.
It is cleared by Bus RESET or by issuing a Power Off primitive.
00 0 This bit is READ ONLY and will always read as a zero.
4.1.2.2 Control and Status Register 1 (CSR1)
RAP <3:1> = 1
15 UERR USER PRIMITIVE ERROR is set by the MK50H27 when a primitive is
issued by the user which is in conflict with the current status of the link.
UERR is READ/CLEAR ONLY and is set by MK50H27 and cleared by
writing a "1" into the bit. Writing a "0" in this bit has no effect. It is
also cleared by Bus RESET.
14 UAV USER PRIMITIVE AVAILABLE is set by the user when a primitive is
written into UPRIM. It is cleared by the MK50H27 after the primitive
has been processed. This bit is also cleared by a Bus RESET.
13:08 UPRIM USER PRIMITIVE is written by the user, in conjunction with setting
UAV, to control the MK50H27 link procedures. The following primitives
are available:
0 Power Off: causes the MK50H27 to enter the Power Off state. All DMA
activity ceases, the transmitter transmits all ones, and all received
data is ignored. Valid in all states except Power Off. Power On: valid only in the Power Off phase and must be issued after
the Init primitive and prior to the Start primitive. Causes the MK50H27
to exit the Power Off phase and to enter the Out of Service phase and
to continuously transmit SIOS signal units. Init: instructs the MK50H27 to read the initialization block from memory.
Valid only in the Power Off mode. Trans: instructs the MK50H27 to enter the HDLC Transparent phase of
operation. Data frames are transmitted and received out of the de-
scriptor rings but no protocol processing is done. Address and
Control fields are not prepended to the frames, but CK processing
works normally. HDLC Transparent Mode may be exited only with a
Power Off primitive or by a bus RESET. Valid only in the Power Off
phase. Status Request: instructs the MK50H27 to write the current link status
into the STATUS BUFFER. Valid in all states, but only after
the Init primitive has been previously issued. Self-Test Request: instructs the MK50H27 to perform the built in
internal self test. Valid only in the Power Off phase. See section 4.4.8
for the self test procedure. Stop: forces all DMA activity to cease. Causes the MK50H27 to enter the
Out of Service phase and to continuously transmit SIOS signal units.
Valid in all phases except the Power Off and Out of Service phase. Start: initial alignment begins and the descriptor rings are reset. Start
should only be issued when in the Out of Service phase, after the in-
itialization block has been read. Local Processor Outage: issued to the MK50H27 to indicate that level
3 or higher levels cannot accept signalling messages. All subsequent
MSU’s are ignored by the MK50H27 & SIPO signal units are transmit-
ted. Local Processor Recovered: indicates end of Local Processor Outage
condition. The MK50H27 may resume transmitting FISUs and MSUs. Emergency: indicates that the emergency proving period is to be used
for initial alignment. Emergency Ceases: Indicates that the normal proving period is to be
used for initial alignment (this is the default proving period). Retrieve BSNT: causes the entire STATUS BUFFER to be updated
including the last transmitted Backward Sequence Number (BSNT).
When completed, PPRIM 18 will be issued. Retrieval request and FSNC: indicates that the FSNC has been
written to the Status Buffer and requests the MK50H27 to update the
retransmission buffer. The MK50H27 should then place the up-
dated retransmission index into the Status Buffer. Congestion: causes the MK50H27 to enter a congestion state and send
SIB signal units at T5 timer interval. It is recommended that the DRX
bit in CSR0 also be set when issuing this primitive so that MSUs can-
not be received during congestion. Clear Congestion: This primitive should be used only to clear the
Congestion state caused by UPRIM 14. If DRX is set, it should be
cleared just prior to issuing this primitive. If congestion state was en-
tered due to a MISSed signal unit then the congestion state should be
cleared by clearing MISS. Start Sending SIOS: If JSS7E=1, this primitive can be used to resume
sending of SIOS signal units, stopped by issuance of UPRIM 17. Valid
only in Out Of Service phase when JSS7E=1 (CSR2). Stop Sending SIOS: If JSS7E=1, this primitive can be used to stop the
transmission of SIOS signal units while the MK50H27 is in the Out of
Service phase. TTC specification JT-Q703 requires that transmission
of SIOS stop some period of time after going Out Of Service; this primi-
tive provides the mechanism for meeting that requiremnt. Transmis-
18/56
sion of SIOS can be resumed by issuing UPRIM 16 described above.
Valid only in Out Of Service phase when JSS7E=1 (CSR2).
07 PLOST PROVIDER PRIMITIVE LOST is set by MK50H27 when a provider
primitive cannot be issued because the PAV bit is still set from the pre-
vious provider primitive. PLOST is cleared when PAV is cleared and
by a Bus RESET. Writing to this bit has no affect.
06 PAV PROVIDER PRIMITIVE AVAILABLE is set by the MK50H27 when a
new provider primitive has been placed in PPRIM. PPRIM is
READ/CLEAR ONLY and is set by the chip and cleared by writing a "1"
to the bit or by Bus RESET. Under normal operation the host should
clear the PAV bit after PPRIM is read.
05:00 PPRIM PROVIDER PRIMITIVE is written by the MK50H27, in conjunction
with setting the PAV bit, to inform the user of link control condi-
tions. Valid Provider Primitives are as follows: Init Confirmation: indicates that the initialization has completed. In Service: indicates that alignment has completed successfully. In Service Yellow: indicates alignment completed succesfully with CCITT
Yellow Book definitions for SINs & SIEs (SF = 9 & 10 respectively).
This primitive will occur only if enabled by RYEL=1 in Protocol Options. Transmit Clock Watchdog Timer Expired: indicates that the watchdog
timer for TCLK has expired due to no transition on TCLK for more than
the number of SYSCLK cycles as selected by CSR4<15:14>. Receive Clock Watchdog Timer Expired: indicates that the watchdog
timer for RCLK has expired due to no transition on RCLK for more than
the number of SYSCLK cycles as selected by CSR4<13:12>. Received SU Timer timeout: indicates that no signal units have been
received within the previous 32xTP time (where TP is the poll timer).
This primitive is only issued if RSUTE=1 (CSR2<12>). Alignment Out of Service: indicates that a transfer to Out of Service
phase has occured, due to an alignment failure. Alignment will fail if
AERM is exceeded, timer T2 times out, or timer T3 times out. LSSU Out of Service: indicates that a transfer to the Out of Service
phase has occured, due to a received LSSU. T1 Out of Service: indicates that a transfer to the Out of Service
phase has occured, due to a timer T1 time out. Transmit Out of Service: indicates that a transfer to the Out of
Service phase has occured, due to a transmit link failure. The trans-
mit link will fail if timers T6 or T7 time out. 12 Receive Out of Service: indicates that a transfer to the Out of Service
phase has occured due to receive link failure. A receive link failure will
occur when more than 2 out of 3 signal units have a FIB or BSN error. SUERM Out of Service: indicates that a transfer to the Out of Service
phase has occured, due to SUERM being exceeded. Remote Processor Outage: indicates that a SIPO has been received
indicating that a remote processor outage condition has occured. Remote Processor Outage Recovered: an FISU or an MSU has been
received since remote processor outage condition has been reported. Received message BSNT: indicates that the MK50H27 has written the
BSNT to the Status Buffer as requested by UPRIM 12. Retrieval complete: retrieval request and FSNC completed successfully.
The pointer to the retransmission buffer is available in STATUS buffer. Remote Processor Busy: an SIB has been received indicating that
the remote node has entered into congestion. Remote Processor Busy Recovered: the remote node has acknowledged
the receipt of an MSU after having entered congestion. This primitive
indicates that the remote node congestion has abated.
4.1.2.3 Control and Status Register 2 (CSR2)
RAP<3:1> = 2 CYCLE Setting this bit selects a shorter DMA cycle (5 vs 6 SYSCLKs for bursting
or 5 vs 7 SYSCLKs for single DMA). See Figures 7a and 8a for details. ESEN Extended Scaler Enable. Setting this bit enables the use of the 16-bit
timer pre-scaler at IADR+24 rather than the 8-bit Scaler at IADR+02.
Using the 16-bit Scaler allows longer timer values at higher SYSCLK
rates. Set ESEN=0 for backward compatibility with the MK50H27. 0 Reserved, must be written as zeroes. RSUTE Received SU Timer Enable. Setting this bit enables a timer for detecting
more than 32xTP time between received Signal Units. If RSUTE=1,
PPRIM=5 will be issued upon expiry of the Received SU Timer. A typi-
cal use for RSUT is to detect breaking of the serial data connection.
11:09 0 Reserved, must be written as zeroes. JSS7E Japanese SS7 Enable. Setting this bit enables TTC JT-Q703 compliance.
When JSS7E=1 the MK50H27 will align using only SIEs, timers Tf, Ts,
To, Ta, and Te will be activated appropriately, and the SUERM will act
in accordance with JT-Q703 requiring interchanging the location of the
T and D fields in the Initialization Block. If JSS7E=1 the MK50H27 will
NOT comply with all CCITT/ITU, ANSI, or AT&T specifications.
07:00 IADR The high order 8 bits of the address of the first word (lowest address)
in the Initialization Block. IADR must be written by the Host
prior to issuing an INIT primitive.
4.1.2.4 Control and Status Register 3 (CSR3)
RAP<3:1> = 3
15:00 IADR The low order 16 bits of the address of the first word (lowest address)
in the Initialization Block. Must be written by the Host prior to issu-
ing an INIT primitive. The Initialization block must begin on a word
boundary.
20/56
4.1.2.5 Control and Status Register 4 (CSR4)
CSR4 allows redefinition of the bus master interface.
RAP<3:1> = 4
15:12 XWD0/1, RWD0/1 These bits enable and determine the timer values for the Transmit and
Receive Watchdog Timers. These timers are independently program-
mable and are reset by any transition on the TCLK and RCLK pins re-
spectively. The Watchdog timers will expire after approximately Wn
SYSCLK cycles (if not reset by transition on TCLK / RCLK pins) and
Provider Primitive 3 or 4 will be issued. The following table shows the
selections for Wn:
XWD1/RWD1 XWD0/RWD0 Wn 0 Disabled 218 219 220
11:10 0 Reserved, must be written as zero.
09:08 FWM These bits define the FIFO watermarks. FIFO watermarks prevent
the MK50H27 from performing DMA transfers to/from the data buffers
until the FIFOs contain a minimum amount of data or space for data.
For receive data, data will only be transferred to the data buffers
after the FIFO has at least N 16-bit words or an end of signal unit
has been reached. Conversely, for transmit data, data will
only be transferred from the data buffers when the transmit FIFO
has room for at least N words of data. N is defined as follows:
11 1 word
10* 9 words
01 17 words
00 25 words
* Suggested setting
07 BAE Bus Address Enable: if BAE is set then the A23-A20 pins are driven
by the MK50H27 constantly providing the ability to use A23-A20 for
memory bus selection. If clear, A23-A20 behave identically to A19-
A16.
06 BUSR If this bit is set, pin 15 becomes input BUSREL. If this bit is clear
then pin 15 is either BM0 or BYTE depending on bit 00. For more
information see the description for pin 15 in this document. BUSR
is READ/WRITE and cleared on bus Reset.
05 BSWPC This bit determines the byte ordering of all "non-data" DMA transfers.
"Non-data DMA transfers refers to any DMA transfers that access
memory other than the data buffers themselves. This includes the
Initialization Block, Descriptors, and Status Buffer. It has no effect
on data DMA transfers. BSWPC allows the MK50H27 to operate with
memory organizations that have bits 07:00 at even addresses and
with bits 15:08 at odd addressses or vice versa. BSWPC is
Read/Write and cleared by BUS RESET.
With BSWPC = 1:
Address Address
This memory organization is used with the 8086 family of microproces-
sors.
With BSWPC = 0:
This memory organization is used with the 68000 and the Z8000
microprocessors.
04:03 BURST This field determines the maximum number of data transfers
performed each time control of the host bus is obtained. BURST
is READ/WRITE and cleared on bus Reset.
* Suggested setting
02 BSWPD This bit determines the byte ordering of all data DMA transfers.
Data transfers are those to or from a data buffer. BSWPD has no ef-
fect on non-data transfers. The effect of BSWPD on data transfers is
the same as that of BSWPC on non-data transfers (see
above). For most applications, including most 68000 based sys-
tems, this bit should be set.
01 ACON ALE CONTROL defines the assertive state of pin 18 when the
MK50H27 is a Bus Master. ACON is READ/ WRITE and cleared by
Bus RESET.
00 BCON BYTE CONTROL redefines the Byte Mask and Hold I/O pins.
BCON is READ/WRITE and cleared by Bus RESET.
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4.1.2.6 Control and Status Register 5 (CSR5)
CSR5 facilitates control and monitoring of modem controls.
RAP<3:1> = 5
15:05 0 Reserved, must be written as zeroes. RTSEN RTS/CTS ENABLE is a READ/WRITE bit used to configure pins 26 is set, pin 26 becomes RTS and pin 30 becomes
CTS. RTS is driven low whenever the MK50H27 has data to trans-
mit and is kept low during transmission. RTS will be driven high
after the closing flag of a signal unit is transmited if either no other
frames are in the FIFO or if the minimum signal unit spacing is
higher than 2 (see Mode Register). The MK50H27 will not begin
transmission and TD will remain HIGH if CTS is high. If RTSEN = 0
then pins 26 and 30 become programmable I/O pins DTR and
DSR. The direction and behavior of DSR and DTR are controlled by
the following bits. DTRD DTR DIRECTION is a READ/WRITE bit used to control the direction
of the DTR pin. If DTRD = 0, the DTR pin becomes an input pin and
the DTR bit reflects the current value of the pin; if DTRD = 1, the DTR
pin is an output pin controlled by the DTR bit below. DSRD DSR DIRECTION is a READ/WRITE bit used to control the direction
of the DSR pin. If DSRD = 0, the DSR pin becomes an input pin
and the DSR bit reflects the current value of the pin; if DSRD = 1, the
DSR pin is an output pin controlled by the DSR bit below. DTR DATA TERMINAL READY is used to control or observe the DTR I/O
pin depending on the value of DTRD. If DTRD = 0, this bit be-
comes READ ONLY and always equals the current value of the DTR
pin. If DTRD = 1, this bit becomes READ/WRITE and any value
written to this bit appears on the DTR pin. DSR DATA SET READY is used to control or observe the DSR I/O
pin depending on the value of DSRD. If DSRD = 0, this bit be-
comes READ ONLY and always equals the current value of the DSR
pin. If DSRD = 1 this bit becomes READ/WRITE and any value
written to this bit appears on the DSR pin.
4.2 Initialization Block
MK50H27 initialization includes the reading of the initialization block in memory to obtain the
operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, por-
tions of the Initialization block are read by the MK50H27. The remainder of the Initialization block
will be read as needed by the MK50H27.BASE ADDRESS
HIGHER ADDR
IADR+00
IADR+02
IADR+26
IADR+36
IADR+38
IADR+40
IADR+42
IADR+44
IADR+50
THRU
IADR+198
Figure 4: Initialization Block
24/56
The Mode Register allows alteration of the MK50H27’s operating parameters.
15:11 MFS<4:0> Minimum Frame Spacing defines the minimum number of flag
sequences transmitted between adjacent frames transmitted by the
MK50H27. This only affects frames transmitted by the MK50H27
and does not restrict the spacing of the frames received by the
MK50H27. When using RTS/CTS control this field defines the
CTS is driven low (minus one for the trailing flag). See the fol-
lowing table for encoding of this field.
10 EXTCF Extended Control Force. Must be reset to zero for both SS7 and HDLC
transparent mode
09 EXTAF Extended Address Force. If set along with EXTA, the receiver will
assume the address to be two otets long regardless of the first bit of
the address. See EXTA below. Must be set to a 1 for SS7 operation.
Must be reset to a zero for HDLC transparent mode. DACE Disable Address and Control field Extraction. DACE should be written
with "0" for normal SS7 operation and with "1" for HDLC Transparent
mode. The MK50H27 however, has a feature to allow shifting of the
alignment of the data in the MSU buffers. If DACE is set to "1" for SS7
mode, the received LI will be placed in the first byte of the receive buff-
er, followed by the SIO in the second byte and so on. If DACE = 1, on
transmit the LI must be placed in the first byte of the transmit buffer
rather than in the SUL field of the Transmit Descriptor Entry (TMD2).
07 EXTC Extended Control Field. Must be reset to zero for both SS7 and HDLC
transparent mode. EXTA Extended address Field. Must be set to a 1 for SS7 operation. Must
be reset to a zero for HDLC transparent mode.
IADR + 00
05 DRCK Disable Receiver CK. When DRCK = 0, the receiver will extract
and check the CK field at the end of each signal unit. When
DRCK = 1, the receiver continues to extract the last 16 or 32 bits of
each signal unit, depending on CKS, but no check is performed to
determine whether the CK is correct. The CK is not stored into the
Receive buffer.
04 DTCK Disable Transmitter CK. When DTCK = 0, the transmitter will
generate and append the CK to each signal unit. When DTCK = 1,
the CK logic is disabled, and no CK is generated with transmitted sig-
nal units. Setting DTCK=1 is useful in loopback testing for check-
ing the ability of the receiver to detect an incorrect CK.
03 CKS CK Select. When CKS = 1, the 16 bit CK is selected otherwise the
32 bit CK is used.
02:00 LBACK Loopback Control puts the MK50H27 into one of several loopback
configurations.
4.2.2 Timers
There are ten independent counter-timers defined in SS7. The upper 8 bits of IADR+02 are used
as a scaler for T1 through T7, and TP. The scaler is driven by a clock which is 1/32 of SYSCLK. N1 is
the maximum number of signal units allowed for retransmission (transmission window size) and N2 is the
maximum number of bytes allowed for retransmission. The value for N1 is set to 128.
The Host will write the period of N2, T1-T7, and TP into the Initialization Block.
SCALER TIMER PRESCALER. Timers T1-T7 and TP are scaled by this
number. The prescaler is incremented once every 32 system
clock pulses. When it reaches zero the timers are incremented and
the prescaler is reset. This field is interpreted as the two’s comple-
ment of the prescaler period. The MK50H27 multiplies this value
by 16 when it is read into the device. Note: a prescale value of one
gives the smallest amount of scaling to the timers (512 clock pulses),
zero gives the largest (131584 clock pulses).
N2 Octet window size. N2 gives the maximum number of MSU
octets allowed for retransmission. N2 includes the opening and clos-
ing flags, BSN/BIB, FSN/FIB, LI, and the CK octets. This value is
expressed as a positive integer. Bits <14:8> of IADR + 02 represent
the most significant bits of N2. ALIGNED READY TIMER PERIOD. T1 determines the maximum
time the MK50H27 will stay in the ALIGNED READY state before sig-
nalling link failure. Represented as two’s complement.
T2 NOT ALIGNED TIMER PERIOD. T2 determines the maximum time
the MK50H27 will wait in the NOT ALIGNED state before signalling
link failure. Represented as two’s complement.
26/56
T3 ALIGNED TIMEOUT TIMER PERIOD. T3 determines the maximum
time the MK50H27 will wait in the ALIGNED state before signalling link
failure. Represented as two’s complement.
T4n NORMAL PROVING PERIOD. T4n determines the length of the
normal proving period as defined in CCITT Q.703. Represented as
two’s complement.
T4e EMERGENCY PROVING PERIOD. T4e determines the length of the
emergency proving period as defined in CCITT Q.703. Represented
as two’s complement. BUSY TRANSMIT PERIOD. T5 determines the amount of time
the MK50H27 will wait between transmissions of status indication "B"
while in congestion state. Represented as two’s complement.
T6 EXCESSIVE BUSY TIMER PERIOD. T6 determines the amount of
time the MK50H27 will allow a remote site to remain in the congested
state before signalling link failure. Represented as two’s complement. EXCESSIVE ACKNOWLEDGE TIMER PERIOD. T7 determines the
maximum amount of time the MK50H27 will wait for an expected
acknowledgement of an MSU before signalling link failure. Repre-
sented as two’s complement. TRANSMIT POLLING PERIOD. This scaled timer determines the
length of time between transmit signal unit checks. Unless TDMD
(see CSR0) is set or a signal unit is received on the link, no at-
tempt to transmit a signal unit in the transmit descriptor ring is made
until TP expires. At TP expiration all transmit signal units in the
transmit descriptor ring are sent. Represented as two’s complement.
RESERVED/ 16-bit Scaler Can be programmed as all zeroes for compatibliity with existing MK50H27
applications. However, if ESEN=1 (CSR2<14>), then this field is de-
fined as a 16-bit scaler for all of the timers, and it will be used instead
of the Scaler at IADR+02. This prescaler is incremented once every
32 system clock pulses. When it reaches zero the timers are incre-
mented and the prescaler is reset. This field is interpreted as the
two’s complement of the prescaler period. This 16-bit scaler is NOT
multiplied by 16 when read into the MK50H27. FISU Sending Interval timer. This timer, located at IADR + 144 will
determine the amount of time between transmission of FISUs when in
TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Represented as
two’s complement. SIOS Sending Interval timer. This timer, located at IADR + 146 will
determine the amount of time between transmission of SIOS signal
units when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1).
Represented as two’s complement. SIO Sending Interval timer. This timer, located at IADR + 148 will
determine the amount of time between transmission of SIOsignal units
when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Repre-
sented as two’s complement. SIE Sending Interval timer. This timer, located at IADR + 150 will
determine the amount of time between transmission of SIE signal units
when in TTC JT-Q703 compliant mode (CSR2<08> JSS7E=1). Repre-
sented as two’s complement.
Note: The Tf, Ts, To, & Ta timers are only active and valid when JSS7E=1 (CSR2<08>).
IADR + 02
IADR + 04
IADR + 06
IADR + 08
IADR + 10
IADR + 12
IADR + 14
IADR + 16
IADR + 18
IADR + 20
IADR + 22
IADR + 24
28/56

Partno	Mfg	Dc	Qty	Available	Descript
MK50H27		N/a	2	avai	SIGNALLING SYSTEM 7 LINK CONTROLLER