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Unlike conventional shift register based FIFOs, the
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MK45H02N-25-MK45H02N-50-MK45H02N-65
VERY FAST CMOS 512/1K/2K x9BiPORT FIFO
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MK45H01 ,02,03
MK45H11,12,13
VERY FAST CMOS 512/ 1K / 2K X 9 BiPORT FIFO
n FIRST-IN-FIRST-OUT MEMORY BASED
ARCHITECTURE
u FLEXIBLE x 9 ORGANIZATIONS:
- MK45H01,11 (512 x 9)
- MK45H02,12 (1K x 9)
- MK45H03,13 (2K x 9)
II LOW POWER, HIGH SPEED HCMOS TECH-
NOLOGY
ASYNCHRONOUS AND SIMULTANEOUS
READ/WRITE
FULLY EXPANDABLE IN WORD WIDTH AND
EMPTY AND FULL WARNING FLAGS
II RETRANSMIT CAPABILITY
II HALF-FULL FLAG IN SINGLE DEVICE MODE
DESCRIPTION
The MK45HO1,11,02,12,03,13 are BiPOFlTTM FIFO
memories from SGS-THOMSON Microelectronics,
which utilize special two-port memory cell tech-
niques. Specifically, these devices implement a
First-ln-First-Out (FIFO) algorithm, featuring asyn-
chronous read/write operations, full, empty, and
half full status flags, and unlimited expansion ca-
pability in both word size and depth. The full and
empty flags are provided to prevent data overflow and
underflow.
PIN NAMES
W Write
A Read
AS Reset
DO-DB Data Inputs
QO-QS Data Outputs
WB_T First Load / Retransmit
W Expansion Input
WIFE Expansion Output/ Half-full Flag
FT: Full Flag
w: Empty Flag
Vcc, GND 5 Volts, Ground
NC Not Connected
February 1992
PDIP28 (N) PSDIP28 (N)
PLCC32 (K)
Figure 1. Pin Connections
WQ 1 28 l Vcc
D8 I 2 27 l D4
D3t 3 26 J 05
D2 E 4 25 l D6
DIt 5 24 l D7
Dot 6 21 , TL/TT'
XI L 7 22 3 RS
if t a MK45HXX 21 D 7
oo t 9 20 l WA
01!: 10 19 l Q7
Q2 r 11 18 108
03 r " 17 105
08 r 13 16 104
GNDE 14 15 l p
VA00557
2 [fl lit 'd >03 g
4 3 2 , 323130
5 29 J 06
6 28 a 07
7 27 3 NC
a 28 7rTnTr
9 MK45HXX " OR-s
1o " , E
11 23 3 Co T:
12 22 :1 Q7
13 21 J 06
141516 1718 " 20
MK45H01,11,02,12,03,13
Figure 2. Block Diagram
Do- De
BUFFER
OUTPUT
BUFFER
CONTROL
ADDRESS
POINTER
x tt READ _
Biponr"
MEMORY ARRAY
ADDRESS
POINTER CONTROL
- LOGIC
EXPANSION LOGIC
- RESET/RETRANSMIT
VHUUOQEZ
DESCRIPTION (Continued)
The data is loaded and emptied on a first-in-first-out
basis, and the latency for retrieval of data is ap-
proximately one load (write) cycle. These devices
feature a read/write cycle time of only 35ns
(28.5MH2).
The reads and writes are internally sequential
through the use of separate read and write pointers
in a ring counter fashion. Therefore, no address
information is required to load or unload Qata. Data
is logied and unloaded with the use of W (write),
and R (read) input pins. Separate data in (DO-D8)
and data out (00-08) pins allow simultaneous and
asynchronous read/write operations, provided the
status flags are not protecting against data under-
flow or overflow.
The main application of these devices is a buffer
for sourcing and absorbing data at different rates
(e.g., interfacing fast processors and slow periphe-
rals). The MK45HX1, MK45HX2, and MK45HX3 incor-
porate 9-bit wide data arrays that provide for
support control or parity bit functions. This feature
is helpful in data communications where the extra
parity bit is used for transmission and reception
er_ror checking. These devices also offer retransmit
(RT) and half-full features in single device or width
expansion modes. The retransmit function allows
m SGS-WOMSOH
e Ml0Cl'l@aECTR@WRXl,
data to be re-read by resetting the read pointer
while not disturbing the write pointer. This is for
applications where the FIFO is not full, or is written
with less than 512, 1024, or 2048 words.
FUNCTIONAL DESCRIPTION
Unlike conventional shift register based FIFOs, the
MK45HX1, MK45HX2, and MK45HX3 employ a
memory-based architecture wherein a byte written
into the device does not "ripple through". Instead,
a byte written into the device is stored in a specific
location, where it remains until over-written. The
byte can be read and re-read as often as desired
in the single device configuration.
Two internal pointers (ring counters) automatically
generate the addresses required for each write and
read operation. The empty/full flag circuit prevents
illogical operations, such as reading un-written
bytes (reading while empty) or over-writing un-read
bytes (writing while full). Once a byte stored at a
given address has been read, it can be over-writ-
ten. The address pointers automatically loop back
to address zero after reaching the final address in
the FIFO (512, 1024, or 2048). The empty, half full,
and full status of the FIFO is therefore a function of
the distance between the pointers, not of their
absolute location.
