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MFRC531 01T-MFRC53101T-MFRC531-01T
Standard ISO/IEC 14443 A/B reader solution
1. IntroductionThis data sheet describes the functionality of the MFRC531 Integrated Circuit (IC). It
includes the functional and electrical specifications and from a system and hardware
viewpoint gives detailed information on how to design-in the device.
Remark: The MFRC531 supports all variants of the MIFARE Mini, MIFARE 1K,
MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus RF
identification protocols. To aid readability throughout this data sheet, the MIFARE Mini,
MIFARE 1K, MIFARE 4K, MIFARE Ultralight, MIFARE DESFire EV1 and MIFARE Plus
products and protocols have the generic name MIFARE.
2. General descriptionThe MFRC531 is a highly integrated reader IC for contactless communication at
13.56 MHz. The MFRC531 reader IC provides:
outstanding modulation and demodulation for passive contactless communication
a wide range of methods and protocols
a small, fully integrated package
pin compatibility with the MFRC500, MFRC530 and SLRC400
All protocol layers of the ISO/IEC 14443 A and ISO/IEC 14443 B communication
standards are supported provided:
additional components, such as the oscillator, power supply, coil etc. are correctly
applied.
standardized protocols, such as ISO/IEC 14443-4 and/or ISO/IEC 14443 B
anticollision are correctly implemented
The MFRC531 supports contactless communication using MIFARE higher baud rates
(see Section 9.12 on page 38). The receiver module provides a robust and efficient
demodulation/decoding circuitry implementation for compatible transponder signals (see
Section 9.10 on page 32).
The digital module, manages the complete ISO/IEC 14443 standard framing and error
detection (parity and CRC). In addition, it supports the fast MIFARE security algorithm for
authenticating the MIFARE products (see Section 9.14 on page 40).
The internal transmitter module (Section 9.9 on page 29) can directly drive an antenna
designed for a proximity operating distance up to 100 mm without any additional active
circuitry.
MFRC531
Standard ISO/IEC 14443 A/B reader solution
Rev. 3.6 — 27 February 2014
Product data sheet
COMPANY PUBLIC
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solutionA parallel interface can be directly connected to any 8-bit microprocessor to ensure
reader/terminal design flexibility. In addition, Serial Peripheral Interface (SPI) compatibility
is supported (see Section 9.1.4 on page 9).
3. Features and benefits
3.1 General Highly integrated analog circuitry for demodulating and decoding card/label response Buffered output drivers enable antenna connection using the minimum of external
components Proximity operating distance up to 100 mm Supports both ISO/IEC 14443 A and ISO/IEC 14443 B standards Supports the MIFARE Mini, MIFARE 1K, MIFARE 4K protocols Contactless communication at MIFARE higher baud rates (up to 424 kBd) Crypto1 and secure non-volatile internal key memory Pin-compatible with the MFRC500, MFRC530 and the SLRC400 Parallel microprocessor interface with internal address latch and IRQ line SPI compatibility Flexible interrupt handling Automatic detection of parallel microprocessor interface type 64-byte send and receive FIFO buffer Hard reset with low power function Software controlled Power-down mode Programmable timer Unique serial number User programmable start-up configuration Bit-oriented and byte oriented framing Independent power supply pins for analog, digital and transmitter modules Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz
connection Clock frequency filtering 3.3 V to 5 V operation for transmitter in short range and proximity applications 3.3 V or 5 V operation for the digital module
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
4. Applications Electronic payment systems Identification systems Access control systems Subscriber services Banking systems Digital content systems
5. Quick reference data
6. Ordering information
Table 1. Quick reference data
Table 2. Ordering information
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
7. Block diagramNXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
8. Pinning information
8.1 Pin description
Table 3. Pin description
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution[1] Pin types: I= Input, O= Output, I/O= Input/Output, P= Power and G= Ground.
[2] The SLRC400 uses pin name SIGOUT for pin MFOUT. The MFRC531 functionality includes test functions for the SLRC400 using pin
MFOUT.
[3] These pins provide different functionality depending on the selected microprocessor interface type (see Section 9.1 on page 7 for
detailed information).
Table 3. Pin description …continued
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9. Functional description
9.1 Digital interface
9.1.1 Overview of supported microprocessor interfacesThe MFRC531 supports direct interfacing to various 8-bit microprocessors. Alternatively,
the MFRC531 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows
the parallel interface signals supported by the MFRC531.
9.1.2 Automatic microprocessor interface detectionAfter a Power-On or Hard reset, the MFRC531 resets parallel microprocessor interface
mode and detects the microprocessor interface type.
The MFRC531 identifies the microprocessor interface using the logic levels on the control
pins. This is performed using a combination of fixed pin connections and the dedicated
Initialization routine (see Section 9.7.4 on page 28).
Table 4. Supported microprocessor and EPP interface signals
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.1.3 Connection to different microprocessor typesThe connection to various microprocessor types is shown in Table5.
9.1.3.1 Separate read and write strobeRefer to Section 13.4.1 on page 93 for timing specification.
Table 5. Connection scheme for detecting the parallel interface type
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.1.3.2 Common read and write strobeRefer to Section 13.4.2 on page 94 for timing specification.
9.1.3.3 Common read and write strobe: EPP with handshakeRefer to Section 13.4.3 on page 95 for timing specification.
Remark: In the EPP standard, a chip select signal is not defined. To cover this situation, the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not
used, it is mandatory that pin NCS is connected to pin DVSS.
Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after
the reset phase. The MFRC531 does not support the Read Address Cycle.
9.1.4 Serial Peripheral InterfaceThe MFRC531 provides compatibility with the 5-wire Serial Peripheral Interface (SPI)
standard and acts as a slave during SPI communication. The SPI clock signal SCK must
be generated by the master. Data communication from the master to the slave uses the
MOSI line. The MISO line sends data from the MFRC531 to the master.
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solutionFigure 6 shows the microprocessor connection to the MFRC531 using SPI.
Remark: The SPI implementation for MFRC531 conforms to the SPI standard and ensures that the MFRC531 can only be addressed as a slave.
9.1.4.1 SPI read dataThe structure shown in Table 7 must be used to read data using SPI. It is possible to read
up to n-data bytes. The first byte sent defines both, the mode and the address.
The address byte must meet the following criteria:
the Most Significant Bit (MSB) of the first byte sets the mode. To read data from the
MFRC531 the MSB is set to logic 1
bits [6:1] define the address
the Least Significant Bit (LSB) should be set to logic 0.
As shown in Table 8, all the bits of the last byte sent are set to logic 0.
Table 6. SPI compatibility
Table 7. SPI read data
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution[1] All reserved bits must be set to logic 0.
9.1.4.2 SPI write dataThe structure shown in Table 9 must be used to write data using SPI. It is possible to write
up to n-data bytes. The first byte sent defines both the mode and the address.
The address byte must meet the following criteria:
the MSB of the first byte sets the mode. T o write data to the MFRC531, the MSB is set
to logic 0
bits [6:1] define the address
the LSB should be set to logic 0.
SPI write mode writes all data to the address defined in byte 0 enabling effective write
cycles to the FIFO buffer.
[1] All reserved bits must be set to logic 0.
Remark: The data bus pins D7 to D1 must be disconnected.Refer to Section 13.4.4 on page 97 for the timing specification.
Table 8. SPI read address
Table 9. SPI write data
Table 10. SPI write address
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.2 Memory organization of the EEPROM
Table 11. EEPROM memory organization diagram
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.2.1 Product information field (read only)
[1] Byte 4 contains the current version number.
9.2.2 Register initialization files (read/write)
Register initialization from address 10h to address 2Fh is performed automatically during
the initializing phase (see Section 9.7.3 on page 28) using the StartUp register
initialization file.
In addition, the MFRC531 registers can be initialized using values from the register
initialization file when the LoadConfig command is executed (see Section 11.4.1 on
page 86).
Table 12. Product information field
Table 13. Product type identification definition
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
Remark: The following points apply to initialization: the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. make sure that all PreSetxx registers are not changed. make sure that all register bits that are reserved are set to logic 0.
9.2.2.1 StartUp register initialization file (read/write)
The EEPROM memory block address 1 and 2 contents are used to automatically set the
register subaddresses 10h to 2Fh during the initialization phase. The default values stored
in the EEPROM during production are shown in Section 9.2.2.2 “Factory default StartUp
register initialization file”.
The byte assignment is shown in Table 14.
9.2.2.2 Factory default StartUp register initialization file
During the production tests, the StartUp register initialization file is initialized using the
default values shown in Table 15. During each power-up and initialization phase, these
values are written to the MFRC531’s registers.
Table 14. Byte assignment for register initialization at start-up
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solutionTable 15. Shipment content of StartUp configuration file
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.2.2.3 Register initialization file (read/write)
The EEPROM memory content from block address 3 to 7 can initialize register sub
addresses 10h to 2Fh when the LoadConfig command is executed (see Section 11.4.1 on
page 86). This command requires the EEPROM starting byte address as a two byte
argument for the initialization procedure.
The byte assignment is shown in Table 16.
The register initialization file is large enough to hold values for two initialization sets and
up to one block (16-byte) of user data.
Remark: The register initialization file can be read/written by users and these bytes can
be used to store other user data.
After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443A
protocol.
9.2.3 Crypto1 keys (write only)
MIFARE security requires specific cryptographic keys to encrypt data stream
communication on the contactless interface. These keys are called Crypto1 keys.
9.2.3.1 Key format
Keys stored in the EEPROM are written in a specific format. Each key byte must be split
into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble).
Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This
format is a precondition for successful execution of the LoadKeyE2 (see Section 11.6.1 on
page 88) and LoadKey commands (see Section 11.6.2 on page 88).
Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is
shown in Figure7.
Example: The value for the key must be written to the EEPROM. If the key was: A0h A1h A2h A3h A4h A5h then: 5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written.
Table 16. Byte assignment for register initialization at startup
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
Remark: It is possible to load data for other key formats into the EEPROM key storage
location. However, it is not possible to validate card authentication with data which will
cause the LoadKeyE2 command (see Section 11.6.1 on page 88) to fail.
9.2.3.2 Storage of keys in the EEPROM
The MFRC531 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No
memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every
byte of the dedicated memory area can be the start of a key.
Example: If the key loading cycle starts at the last byte address of an EEPROM block, (for
example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM
block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah.
Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32
different keys can be stored in the EEPROM.
Remark: It is not possible to load a key exceeding the EEPROM byte location 1FFh.
9.3 FIFO buffer
An 8 64 bit FIFO buffer is used in the MFRC531 to act as a parallel-to-parallel converter.
It buffers both the input and output data streams between the microprocessor and the
internal circuitry of the MFRC531. This makes it possible to manage data streams up to
64 bytes long without needing to take timing constraints into account.
9.3.1 Accessing the FIFO buffer
9.3.1.1 Access rules
The FIFO buffer input and output data bus is connected to the FIFOData register. Writing
to this register stores one byte in the FIFO buffer and increments the FIFO buffer write
pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO
buffer read pointer and increments the FIFO buffer read pointer. The distance between the
write and read pointer can be obtained by reading the FIFOLength register.
When the microprocessor starts a command, the MFRC531 can still access the FIFO
buffer while the command is running. Only one FIFO buffer has been implemented which
is used for input and output. Therefore, the microprocessor must ensure that there are no
inadvertent FIFO buffer accesses. Table 17 gives an overview of FIFO buffer access
during command processing.
Table 17. FIFO buffer access
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.3.2 Controlling the FIFO buffer
In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
9.3.3 FIFO buffer status information
The microprocessor can get the following FIFO buffer status data: the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0] the FIFO buffer full warning: bit HiAlert the FIFO buffer empty warning: bit LoAlert the FIFO buffer overflow warning: bit FIFOOvfl.
Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.
The MFRC531 can generate an interrupt signal when: bit LoAlertIRq is set to logic 1 and bit LoAlert= logic 1, pin IRQ is activated. bit HiAlertIRq is set to logic 1 and bit HiAlert= logic 1, pin IRQ activated.
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by Equation1:
(1)
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by Equation2:
(2)
Table 17. FIFO buffer access …continued
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.3.4 FIFO buffer registers and flags
Table 17 shows the related FIFO buffer flags in alphabetic order.
9.4 Interrupt request system
The MFRC531 indicates interrupt events by setting the PrimaryStatus register bit IRq (see
Section 10.5.1.4 “PrimaryStatus register” on page 49) and activating pin IRQ. The signal
on pin IRQ can be used to interrupt the microprocessor using its interrupt handling
capabilities ensuring efficient microprocessor software.
9.4.1 Interrupt sources overview
Table 19 shows the integrated interrupt flags, related source and setting condition. The
interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows: the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady= logic 1 when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit
E2Ready= logic 1
The RxIRq flag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq flag bit is set when a command finishes and the content of the Command
register changes to Idle.
When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 18) and bit HiAlert= logic 1, then the HiAlertIRq flag bit is set to
logic1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 18) and bit LoAlert= logic 1, then LoAlertIRq flag bit is set to
logic1.
Table 18. Associated FIFO buffer registers and flags
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.4.2 Interrupt request handling
9.4.2.1 Controlling interrupts and getting their status
The MFRC531 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
If any interrupt request flag is set to logic 1 (showing that an interrupt request is pending)
and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is
set to logic 1. Different interrupt sources can activate simultaneously because all interrupt
request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ.
9.4.2.2 Accessing the interrupt registers
The interrupt request bits are automatically set by the MFRC531’s internal state
machines. In addition, the microprocessor can also set or clear the interrupt request bits
as required.
A special implementation of the InterruptRq and InterruptEn registers enables changing
an individual bit status without influencing any other bits. If an interrupt register is set to
logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. If a
specific interrupt flag is cleared, zero must be written to the SetIxx and the interrupt
register address must be set to logic 1 at the same time.
If a content bit is not changed during the setting or clearing phase, zero must be written to
the specific bit location.
Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0
while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq
to logic 1 and leaves all other bits unchanged.
Table 19. Interrupt sources
Table 20. Interrupt control registers
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.4.3 Configuration of pin IRQ
The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be
controlled using the following IRQPinConfig register bits. bit IRQInv: the signal on pin IRQ is equal to the logic level of bit IRq when this bit is set
to logic 0. When set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq. bit IRQPushPull: when set to logic 1, pin IRQ has CMOS output characteristics. When
it is set to logic 0, it is an open-drain output which requires an external resistor to
achieve a HIGH-level at pin IRQ.
Remark: During the reset phase (see Section 9.7.2 on page 28) bit IRQInv is set to
logic 1 and bit IRQPushPull is set to logic 0. This results in a high-impedance on pin IRQ.
9.4.4 Register overview interrupt request system
Table 21 shows the related interrupt request system flags in alphabetical order.
Table 21. Associated Interrupt request system registers and flags
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.5 Timer unit
The timer derives its clock signal from the 13.56 MHz on-board chip clock. The
microprocessor can use this timer to manage timing-relevant tasks.
The timer unit can be used in one of the following configurations: Timeout counter WatchDog counter Stopwatch Programmable one shot Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific timed event occurred. The timer is triggered by events but does not
influence any event (e.g. a time-out during data receiving does not automatically influence
the receiving process). Several timer related flags can be set and these flags can be used
to generate an interrupt.
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.5.1 Timer unit implementation
9.5.1.1 Timer unit block diagram
Figure 8 shows the block diagram of the timer module.
The timer unit is designed, so that events when combined with enabling flags start or stop
the counter. For example, setting bit TStartTxBegin= logic 1 enables control of received
data with the timer unit. In addition, the first received bit is indicated by the TxBegin event.
This combination starts the counter at the defined TReloadValue[7:0].
The timer stops automatically when the counter value is equal to zero or if a defined stop
event happens. Controlling the timer unit
The main part of the timer unit is a down-counter. As long as the down-counter value is
not zero, it decrements its value with each timer clock cycle.
If the TAutoRestart flag is enabled, the timer does not decrement down to zero. On
reaching value 1, the timer reloads the next clock function with the TReloadValue[7:0].
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
The timer is started immediately by loading a value from the TimerReload register into the
counter module.
This is activated by one of the following events: transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic1 transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd= logic1 bit TStartNow is set to logic 1 by the microprocessor
Remark: Every start event reloads the timer from the TimerReload register. Thus, the
timer unit is re-triggered.
The timer can be configured to stop on one of the following events: receipt of the first valid bit from the card (RxBegin event) with bit
TStopRxBegin= logic1 receipt of the last bit from the card (RxEnd event) with bit TStopRxEnd= logic1 the counter module has decremented down to zero and bit TAutoRestart= logic0 bit TStopNow is set to logic 1 by the microprocessor.
Loading a new value, e.g. zero, into the TimerReload register or changing the timer unit
while it is counting will not immediately influence the counter. This is because this register
only affects the counter content after a start event.
If the counter is stopped when bit TStopNow is set, no TimerIRq is flagged.
9.5.1.3 Timer unit clock and period
The timer unit clock is derived from the 13.56 MHz on-board chip clock using the
programmable divider. Clock selection is made using the TimerClock register
TPreScaler[4:0] bits based on Equation3:
(3)
The values for the TPreScaler[4:0] bits are between 0 and 21 which results in a minimum
periodic time (TTimerClock) of between 74 ns and 150 ms.
The time period elapsed since the last start event is calculated using Equation4:
(4)
This results in a minimum time period (tTimer) of between 74 ns and 40 s.
9.5.1.4 Timer unit status
The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start
events start the timer at the TReloadValue[7:0] and changes the status flag TRunning to
logic 1. Conversely, configured stop events stop the timer and set the TRunning status
flag to logic 0. As long as status flag TRunning is set to logic 1, the TimerValue register
changes on the next timer unit clock cycle.
The TimerValue[7:0] bits can be read directly from the TimerValue register.
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.5.2 Using the timer unit functions
9.5.2.1 Time-out and WatchDog counters
After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue
register beginning with a given start event. If a given stop event occurs, such as a bit
being received from the card, the timer unit stops without generating an interrupt.
If a stop event does not occur, such as the card not answering within the expected time,
the timer unit decrements down to zero and generates a timer interrupt request. This
signals to the microprocessor the expected event has not occurred within the given time
(tTimer).
9.5.2.2 Stopwatch
The time (tTimer) between a start and stop event is measured by the microprocessor using
the timer unit. Setting the TReloadValue register triggers the timer which in turn, starts to
decrement. If the defined stop event occurs, the timer stops. The time between start and
stop is calculated by the microprocessor using Equation 5, when the timer does not
decrement down to zero.
(5)
9.5.2.3 Programmable one shot timer and periodic trigger
Programmable one shot timer: The microprocessor starts the timer unit and waits for
the timer interrupt. The interrupt occurs after the time specified by tTimer.
Periodic trigger: If the microprocessor sets the TAutoRestart bit, it generates an interrupt
request after every tTimer cycle.
9.5.3 Timer unit registers
Table 22 shows the related flags of the timer unit in alphabetical order.
Table 22. Associated timer unit registers and flags
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.6 Power reduction modes
9.6.1 Hard power-down
Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pads and
defined internally (except pin RSTPD itself). The output pins are frozen at a given value.
The status of all pins during a hard power-down is shown in Table 23.
9.6.2 Soft power-down mode
Soft power-down mode is entered immediately using the Control register bit PowerDown.
All internal current sinks, including the oscillator buffer, are switched off. The digital input
buffers are not separated from the input pads and keep their functionality. In addition, the
digital output pins do not change their state.
After resetting the Control register bit PowerDown, the bit indicating Soft power-down
mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The
PowerDown bit is automatically cleared when the Soft power-down mode is exited.
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
Table 23. Signal on pins during Hard power-down
NXP Semiconductors MFRC531
Standard ISO/IEC 14443 A/B reader solution
9.6.3 Standby mode
The Standby mode is immediately entered when the Control register StandBy bit is set. All
internal current sinks, including the internal digital clock buffer are switched off. However,
the oscillator buffer is not switched off.
The digital input buffers are not separated by the input pads, keeping their functionality
and the digital output pins do not change their state. In addition, the oscillator does not
need time to wake-up.
After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for
Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is
automatically cleared when the Standby mode is exited.
9.6.4 Automatic receiver power-down
It is a power saving feature to switch off the receiver circuit when it is not needed. Setting
bit RxAutoPD= logic 1, automatically powers down the receiver when it is not in use.
Setting bit RxAutoPD= logic 0, keeps the receiver continuously powered up.
9.7 StartUp phase
The events executed during the StartUp phase are shown in Figure9.
9.7.1 Hard power-down phase
The hard power-down phase is active during the following cases: a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated
when VDDD or VDDA is below the digital reset threshold. a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100 s (tPD 100 s). Shorter phases will not
necessarily result in the reset phase (treset). The rising or falling edge slew rate on pin
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
Remark: In case two, HIGH level on pin RSTPD, has to be at least 100 s long (tPD 100 s). Shorter phases will not necessarily result in the reset phase treset. The slew rate of
rising/falling edge on pin RSTPD is not critical because pin RSTPD is a Schmitt trigger
input.
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9.7.2 Reset phase
The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see Section 10.5 on page 48).
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
9.7.3 Initialization phase
The initialization phase automatically follows the reset phase and takes 128 clock cycles.
During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the
register subaddresses 10h to 2Fh (see Section 9.2.2 on page 13).
Remark: During the production test, the MFRC531 is initialized with default configuration
values. This reduces the microprocessor’s configuration time to a minimum.
9.7.4 Initializing the parallel interface type
A different initialization sequence is used for each microprocessor. This enables detection
of the correct microprocessor interface type and synchronization of the microprocessor’s
and the MFRC531’s start-up. See Section 9.1.3 on page 8 for detailed information on the
different connections for each microprocessor interface type.
During StartUp phase, the command value is set to 3Fh once the oscillator attains clock
frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At
the end of the initialization phase, the MFRC531 automatically switches to idle and the
command value changes to 00h.
To ensure correct detection of the microprocessor interface, the following sequence is
executed: the Command register is read until the 6-bit register value is 00h. On reading the 00h
value, the internal initialization phase is complete and the MFRC531 is ready to be
controlled write 80h to the Page register to initialize the microprocessor interface read the Command register. If it returns a value of 00h, the microprocessor interface
was successfully initialized write 00h to the Page registers to activate linear addressing mode.
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9.8 Oscillator circuit
The clock applied to the MFRC531 acts as a time basis for the synchronous system
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain highest performance, clock jitter must be as small as possible. This is
best achieved by using the internal oscillator buffer with the recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock
quality has been verified. It must meet the specifications described in Section 13.4.5 on
page 97.
Remark: We do not recommend using an external clock source.
9.9 Transmitter pins TX1 and TX2
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly, using minimal passive
components for matching and filtering (see Section 15.1 on page 98). To enable this, the
output circuitry is designed with a very low-impedance source resistance. The TxControl
register is used to control the TX1 and TX2 signals.
9.9.1 Configuring pins TX1 and TX2
TX1 pin configurations are described in Table 24.
TX2 pin configurations are described in Table 25.
Table 24. Pin TX1 configurations
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9.9.2 Antenna operating distance versus power consumption
Using different antenna matching circuits (by varying the supply voltage on the antenna
driver supply pin TVDD), it is possible to find the trade-off between maximum effective
operating distance and power consumption. Different antenna matching circuits are
described in the Application note “MIFARE Design of MFRC500 Matching Circuit and
Antennas”.
9.9.3 Antenna driver output source resistance
The output source conductance of pins TX1 and TX2 can be adjusted between 1 and
100 using the CwConductance register GsCfgCW[5:0] bits.
The output source conductance of pins TX1 and TX2 during the modulation phase can be
adjusted between 1 and 100 using the ModConductance register GsCfgMod[5:0] bits.
The values are relative to the reference resistance (RS(ref)) which is measured during the
production test and stored in the MFRC531 EEPROM. It can be read from the product
information field (see Section 9.2.1 on page 13). The electrical specification can be found
in Section 13.3.3 on page 92.
Table 25. Pin TX2 configurations
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9.9.3.1 Source resistance tableTable 26. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod
MANT = Mantissa; EXP= Exponent.
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9.9.3.2 Calculating the relative source resistance
The reference source resistance RS(ref) can be calculated using Equation6.
(6)
The reference source resistance (RS(ref)) during the modulation phase can be calculated
using ModConductance register’s GsCfgMod[5:0].
9.9.3.3 Calculating the effective source resistance
Wiring resistance (RS(wire)): Wiring and bonding add a constant offset to the driver
resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The
additional resistance for pin TX1 (RS(wire)TX1) can be set approximately as shown in
Equation7.
(7)
Effective resistance (RSx): The source resistances of the driver transistors (RsMaxP
byte) read from the Product Information Field (see Section 9.2.1 on page 13) are
measured during the production test with CwConductance register’s
GsCfgCW[5:0]= 01h.
To calculate the driver resistance for a specific value set in GsCfgMod[5:0], use
Equation8.
(8)
9.9.4 Pulse width
The envelope carries the data signal information that is transmitted to the card. It is an
encoded data signal based on the Miller code. In addition, each pause of the Miller
encoded signal is again encoded as a pulse of a fixed width. The width of the pulse is
adjusted using the ModWidth register. The pulse width (tw) is calculated using Equation9
where the frequency constant (fclk)= 13.56 MHz.
(9)
9.10 Receiver circuitry
The MFRC531 uses an integrated quadrature demodulation circuit enabling it to detect an
ISO/IEC 14443 A or ISO/IEC 14443 B compliant subcarrier signal on pin RX. ISO/IEC 14443 A subcarrier signal: defined as a Manchester coded ASK modulated
signal ISO/IEC 14443 B subcarrier signal: defined as an NRZ-L coded BPSK modulated
ISO/IEC 14443 B subcarrier signal
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The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90 between them. Both resulting subcarrier signals are amplified, filtered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
9.10.1 Receiver circuit block diagram
Figure 11 shows the block diagram of the receiver circuit. The receiving process can be
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see Section 9.10.2.1 on page 33).
The demodulated signal is amplified by an adjustable amplifier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
The signal can be observed on its way through the receiver as shown in Figure 11. One
signal at a time can be routed to pin AUX using the T estAnaSelect register as described in
Section 15.2.2 on page 103.
9.10.2 Receiver operation
In general, the default settings programmed in the StartUp initialization file are suitable for
device to MIFARE card data communication. However, in some environments specific
user settings will achieve better performance.
9.10.2.1 Automatic Q-clock calibration
The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
and a 90 phase-shifted quadrature signal (Q-clock). To achieve the optimum
demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90. After
the reset phase, a calibration procedure is automatically performed.
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Automatic calibration can be set-up to execute at the end of each Transceive command if
bit ClkQCalib= logic 0. Setting bit ClkQCalib= logic 1 disables all automatic calibrations
except after the reset sequence. Automatic calibration can also be triggered by the
software when bit ClkQCalib has a logic 0 to logic 1 transition.
Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or
approximately 4.8 s.
The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift
between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the
phase-shift between the Q-clock and the I-clock is greater than 180.
Remark: The StartUp configuration file enables automatic Q-clock calibration after a reset If bit ClkQCalib= logic 1, automatic calibration is not performed. Leaving this bit set to
logic 1 can be used to permanently disable automatic calibration. It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The
aim could be to disable automatic calibration and set the delay using the software.
Configuring the delay value using the software requires bit ClkQCalib to have been
previously set to logic 1 and a time interval of at least 4.8 s has elapsed. Each delay
value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the
configured delay value is overwritten by the next automatic calibration interval.
9.10.2.2 Amplifier
The demodulated signal must be amplified by the variable amplifier to achieve the best
performance. The gain of the amplifiers can be adjusted using the RxControl1 register
Gain[1:0] bits; see Table 27.
Table 27. Gain factors for the internal amplifier
See Table 83 “RxControl1 register bit descriptions” on page 61 for additional information.
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9.10.2.3 Correlation circuitry
The correlation circuitry calculates the degree of matching between the received and an
expected signal. The output is a measure of the amplitude of the expected signal in the
received signal. This is done for both, the Q and I-channels. The correlator provides two
outputs for each of the two input channels, resulting in a total of four output signals.
The correlation circuitry needs the phase information for the incoming card signal for
optimum performance. This information is defined for the microprocessor using the
BitPhase register. This value defines the phase relationship between the transmitter and
receiver clock in multiples of the BitPhase time (tBitPhase)=1/13.56MHz.
9.10.2.4 Evaluation and digitizer circuitry
The correlation results are evaluated for each bit-half of the Manchester coded signal. The
evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if the
current bit is valid If the bit is valid, its value is identified If the bit is not valid, it is checked to identify if it contains a bit-collision
Select the following levels for optimal using RxThreshold register bits: MinLevel[3:0]: defines the minimum signal strength of the stronger bit-halve’s signal
which is considered valid. CollLevel[3:0]: defines the minimum signal strength relative to the amplitude of the
stronger half-bit that has to be exceeded by the weaker half-bit of the Manchester
coded signal to generate a bit-collision. If the signal’s strength is below this value,
logic 1 and logic 0 can be determined unequivocally.
After data transmission, the card is not allowed to send its response before a preset time
period which is called the frame guard time in the ISO/IEC 14443 standard. The length of
this time period is set using the RxWait register’s RxWait[7:0] bits. The RxWait register
defines when the receiver is switched on after data transmission to the card in multiples of
one bit duration.
If bit RcvClkSelI is set to logic 1, the I-clock is used to clock the correlator and evaluation
circuits. If bit RcvClkSelI is set to logic 0, the Q-clock is used.
Remark: It is recommended to use the Q-clock.
9.11 Serial signal switch
The MFRC531 comprises two main blocks: digital circuitry: comprising the state machines, encoder and decoder logic etc. analog circuitry: comprising the modulator, antenna drivers, receiver and
amplification circuitry
The interface between these two blocks can be configured so that the interface signals
are routed to pins MFIN and MFOUT. This makes it possible to connect the analog part of
one MFRC531 to the digital part of another device.
The serial signal switch can be used to measure MIFARE and ISO/IEC 14443A.
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Remark: Pin MFIN can only be accessed at 106 kBd based on ISO/IEC 14443 A. The
Manchester signal and the Manchester signal with subcarrier can only be accessed on pin
MFOUT at 106 kBd based on ISO/IEC 14443A.
9.11.1 Serial signal switch block diagram
Figure 13 shows the serial signal switches. Three different switches are implemented in
the serial signal switch enabling the MFRC531 to be used in different configurations.
The serial signal switch can also be used to check the transmitted and received data
during the design-in phase or for test purposes. Section 15.2.1 on page 101 describes the
analog test signals and measurements at the serial signal switch.
Remark: The SLR400 uses pin name SIGOUT for pin MFOUT. The MFRC531
functionality includes the test modes for the SLRC400 using pin MFOUT.
Section 9.11.2, Section 9.11.2.1 and Section 9.11.2.2 describe the relevant registers and
settings used to configure and control the serial signal switch.
9.11.2 Serial signal switch registers
The RxControl2 register DecoderSource[1:0] bits define the input signal for the internal
Manchester decoder and are described in Table 28.
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The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the
transmitted 13.56 MHz energy carrier. The modulated signal drives pins TX1 and TX2.
The MFOUTSelect register MFOUTSelect[2:0] bits select the output signal which is to be
routed to pin MFOUT.
To use the MFOUTSelect[2:0] bits, the TestDigiSelect register SignalToMFOUT bit must
be logic 0.
9.11.2.1 Active antenna concept
The MFRC531 analog and digital circuitry is accessed using pins MFIN and MFOUT.
Table 31 lists the required settings.
Table 28. DecoderSource[1:0] values
See Table 93 on page 64 for additional information.
Table 29. ModulatorSource[1:0] values
See Table 93 on page 64 for additional information.
Table 30. MFOUTSelect[2:0] values
See Table 106 on page 67 for additional information.
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[1] The number column refers to the value in the number column of Table 28, Table 29 and Table 30.
Two MFRC531 devices configured as described in Table 31 can be connected to each
other using pins MFOUT and MFIN.
Remark: The active antenna concept can only be used at 106 kBd based on
ISO/IEC 14443A.
9.11.2.2 Driving both RF parts
It is possible to connect both passive and active antennas to a single IC. The passive
antenna pins TX1, TX2 and RX are connected using the appropriate filter and matching
circuit. At the same time an active antenna is connected to pins MFOUT and MFIN. In this
configuration, two RF parts can be driven, one after another, by one microprocessor.
9.12 MIFARE higher baud rates
The MIFARE system is specified with a fixed baud rate of 106 kBd for communication on
the RF interface. The current version of ISO/IEC 14443 A also defines 106 kBd for the
initial phase of a communication between Proximity Integrated Circuit Cards (PICC) and
Proximity Coupling Devices (PCD).
To cover requirements of large data transmissions and to speed up terminal to card
communication, the MFRC531 supports communication at MIFARE higher baud rates in
combination with a microcontroller IC such as the MIFARE ProX.
The MIFARE higher baud rates concept is described in the application note: MIFARE
Implementation of Higher Baud rates Ref. 5. This application note covers the integration
of the MIFARE higher baud rates communication concept in current applications.
Table 31. Register settings to enable use of the analog circuitry
Table 32. MIFARE higher baud rates
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9.13 ISO/IEC 14443 B communication scheme
The international standard ISO/IEC 14443 covers two communication schemes;
ISO/IEC 14443 A and ISO/IEC 14443 B. The MFRC531 reader IC fully supports both
ISO/IEC 14443 variants.
Table 33 describes the registers and flags covered by the ISO/IEC 14443B
communication protocol.
As reference documentation, the international standard ISO/IEC 14443 Identification
cards - Contactless integrated circuit(s) cards - Proximity cards, part 1-4 (Ref. 4) can be
used.
Remark: NXP Semiconductors does not offer a basic function library to design-in the
ISO/IEC 14443 B protocol.
Table 33. ISO/IEC 14443B registers and flags
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9.14 MIFARE authentication and Crypto1
The security algorithm used in the MIFARE products is called Crypto1. It is based on a
proprietary stream cipher with a 48-bit key length. To access data on MIFARE cards,
knowledge of the key format is needed. The correct key must be available in the
MFRC531 to enable successful card authentication and access to the card’s data stored
in the EEPROM.
After a card is selected as defined in ISO/IEC 14443 A standard, the user can continue
with the MIFARE protocol. It is mandatory that card authentication is performed.
Crypto1 authentication is a 3-pass authentication which is automatically performed when
the Authent1 and Authent2 commands are executed (see Section 11.6.3 on page 89 and
Section 11.6.4 on page 89).
During the card authentication procedure, the security algorithm is initialized. After a
successful authentication, communication with the MIFARE card is encrypted.
9.14.1 Crypto1 key handling
On execution of the authentication command, the MFRC531 reads the key from the key
buffer. The key is always read from the key buffer and ensures Crypto1 authentication
commands do not require addressing of a key. The user must ensure the correct key is
prepared in the key buffer before triggering card authentication.
The key buffer can be loaded from: the EEPROM using the LoadKeyE2 command (see Section 11.6.1 on page 88) the microprocessor’s FIFO buffer using the LoadKey command (see Section 11.6.2
on page 88). This is shown in Figure 14.
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9.14.2 Authentication procedure
The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid
authentication, the correct key has to be available in the key buffer of the MFRC531. This
can be ensured as follows: Load the internal key buffer by using the LoadKeyE2 (see Section 11.6.1 on page 88)
or the LoadKey (see Section 11.6.2 on page 88) commands. Start the Authent1 command (see Section 11.6.3 on page 89). When finished, check
the error flags to obtain the command execution status. Start the Authent2 command (see Section 11.6.4 on page 89). When finished, check
the error flags and bit Crypto1On to obtain the command execution status.
10. MFRC531 registers
10.1 Register addressing modes
Three methods can be used to operate the MFRC531: initiating functions and controlling data by executing commands configuring the functional operation using a set of configuration bits monitoring the state of the MFRC531 by reading status flags
The commands, configuration bits and flags are accessed using the microprocessor
interface. The MFRC531 can internally address 64 registers using six address lines.
10.1.1 Page registers
The MFRC531 register set is segmented into eight pages contain eight registers each. A
Page register can always be addressed, irrespective of which page is currently selected.
10.1.2 Dedicated address bus
When using the MFRC531 with the dedicated address bus, the microprocessor defines
three address lines using address pins A0, A1 and A2. This enables addressing within a
page. To switch between registers in different pages a paging mechanism needs to be
used.
Table 34 shows how the register address is assembled.
10.1.3 Multiplexed address bus
The microprocessor may define all six address lines at once using the MFRC531 with a
multiplexed address bus. In this case, either the paging mechanism or linear addressing
can be used.
Table 35 shows how the register address is assembled.
Table 34. Dedicated address bus: assembling the register address
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10.2 Register bit behavior
Bits and flags for different registers behave differently, depending on their functions. In
principle, bits with same behavior are grouped in common registers. Table 36 describes
the function of the Access column in the register tables.
Table 35. Multiplexed address bus: assembling the register address
Table 36. Behavior and designation of register bits
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10.3 Register overviewTable 37. MFRC531 register overview
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Table 37. MFRC531 register overview …continued
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10.4 MFRC531 register flags overview Table 38. MFRC531 register flags overview
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Table 38. MFRC531 register flags overview …continued
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Table 38. MFRC531 register flags overview …continued
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10.5 Register descriptions
10.5.1 Page 0: Command and status
10.5.1.1 Page register
Selects the page register.
10.5.1.2 Command register
Starts and stops the command execution.
Table 39. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h)
reset value: 1000 0000b, 80h bit allocation
Table 40. Page register bit descriptions
Table 41. Command register (address: 01h) reset value: x000 0000b, x0h bit allocation
Table 42. Command register bit descriptions
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10.5.1.3 FIFOData register
Input and output of the 64 byte FIFO buffer.
10.5.1.4 PrimaryStatus register
Bits relating to receiver, transmitter and FIFO buffer status flags.
Table 43. FIFOData register (address: 02h) reset value: xxxx xxxxb, 05h bit allocation
Table 44. FIFOData register bit descriptions
Table 45. PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation
Table 46. PrimaryStatus register bit descriptions
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10.5.1.5 FIFOLength register
Number of bytes in the FIFO buffer.
Table 46. PrimaryStatus register bit descriptions …continued
Table 47. FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation
Table 48. FIFOLength bit descriptions
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10.5.1.6 SecondaryStatus register
Various secondary status flags.
10.5.1.7 InterruptEn register
Control bits to enable and disable passing of interrupt requests.
[1] This bit can only be set or cleared using bit SetIEn.
Table 49. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit
allocation
Table 50. SecondaryStatus register bit descriptions
Table 51. InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation
Table 52. InterruptEn register bit descriptions
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10.5.1.8 InterruptRq register
Interrupt request flags.
[1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq.
Table 53. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation
Table 54. InterruptRq register bit descriptions
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10.5.2 Page 1: Control and status
10.5.2.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 48.
10.5.2.2 Control register
Various control flags, for timer, power saving, etc.
10.5.2.3 ErrorFlag register
Error flags show the error status of the last executed command.
Table 55. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation
Table 56. Control register bit descriptions
Table 57. ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation
Table 58. ErrorFlag register bit descriptions
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[1] Only valid for communication using ISO/IEC 14443 A.
10.5.2.4 CollPos register
Bit position of the first bit-collision detected on the RF interface.
Remark: A bit collision is not indicated in the CollPos register when using the
ISO/IEC 14443 B protocol standard.
Table 58. ErrorFlag register bit descriptions …continued
Table 59. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation
Table 60. CollPos register bit descriptions
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10.5.2.5 TimerValue register
Value of the timer.
10.5.2.6 CRCResultLSB register
LSB of the CRC coprocessor register.
10.5.2.7 CRCResultMSB register
MSB of the CRC coprocessor register.
Table 61. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation
Table 62. TimerValue register bit descriptions
Table 63. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit
allocation
Table 64. CRCResultLSB register bit descriptions
Table 65. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit
allocation
Table 66. CRCResultMSB register bit descriptions
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10.5.2.8 BitFraming register
Adjustments for bit oriented frames.
Table 67. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation
Table 68. BitFraming register bit descriptions
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10.5.3 Page 2: Transmitter and control
10.5.3.1 Page register
Selects the page register; see Section 10.5.1.1 “Page register” on page 48.
10.5.3.2 TxControl register
Controls the logical behavior of the antenna pin TX1 and TX2.
Table 69. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation
Table 70. TxControl register bit descriptions
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10.5.3.3 CwConductance register
Selects the conductance of the antenna driver pins TX1 and TX2.
See Section 9.9.3 on page 30 for detailed information about GsCfgCW[5:0].
10.5.3.4 ModConductance register
Defines the driver output conductance.
Remark: When Force100ASK= logic 1, the GsCfgMod[5:0] value has no effect.
See Section 9.9.3 on page 30 for detailed information about GsCfgMod[5:0].
Table 71. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit
allocation
Table 72. CwConductance register bit descriptions
Table 73. ModConductance register (address: 13h) reset value: 0011 1111b, 3Fh bit
allocation
Table 74. ModConductance register bit descriptions
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10.5.3.5 CoderControl register
Sets the clock rate and the coding mode.
10.5.3.6 ModWidth register
Selects the pulse modulation width.
10.5.3.7 PreSet16 register
Remark: These values must not be changed.
Table 75. CoderControl register (address: 14h) reset value: 0001 1001b, 19h bit allocation
Table 76. CoderControl register bit descriptions
Table 77. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation
Table 78. ModWidth register bit descriptions
Table 79. PreSet16 register (address: 16h) reset value: 0000 0000b, 00h bit allocation
