MF4CWM-100 ,4TH ORDER SWITCHED CAPACITOR BUTTERWORTHElectrical Characteristics The following specifications apply for ICLK s 250 kHz (see Note 5) unles ..
MF4CWM50 ,4TH ORDER SWITCHED CAPACITOR BUTTERWORTHMF4
National
Semiconductor
MF4 4th Order Switched Capacitor Butterworth
Lowpass Filter
..
MF4CWM-50 ,4TH ORDER SWITCHED CAPACITOR BUTTERWORTHapplications, or for tighter cutoff frequency control an
externaI TTL or CMOS logic compatible clo ..
MF5 ,Universal Monolithic Switched Capacitor FilterFeaturesYThe MF5 consists of an extremely easy to use, general pur- Low costpose CMOS active filter ..
MF6CN-100 ,5 V to 14 V, 500 mW, 6-th order switched capacitor butterworth lowpass filter
MF6CWM-100 ,6th Order Switched Capacitor Butterworth Lowpass
MIC5255-3.1BM5 , 150mA Low Noise UCap CMOS LDO
MIC5255-3.1BM5 , 150mA Low Noise UCap CMOS LDO
MIC5255-3.1BM5 , 150mA Low Noise UCap CMOS LDO
MIC5255-3.1BM5 , 150mA Low Noise UCap CMOS LDO
MIC5255-3.1YM5 , 150mA Low Noise UCap CMOS LDO
MIC5255-3.1YM5 , 150mA Low Noise UCap CMOS LDO
MF4CN-100-MF4CWM100-MF4CWM-100-MF4CWM50-MF4CWM-50
4TH ORDER SWITCHED CAPACITOR BUTTERWORTH
gil Natiqnal
1 Semiconductor
MF4 4th Order Switched Capacitor Butterworth
Lowpass Filter
General Descrlptlon
The MF4 Is a versatile. easy to use, precision 4th order
Butterworth low-pass filter. Switehssd-eapattitor techniques
eliminate external component requirements and allow a
clock-tunable cutoff frequency. The ratio of the clock fre-
quency to the low-pass cutoff frequency is internally set to
50 to 1 (MF4-50) or 100 to 1 (MF4-100). A Schmitt trigger
clock input stage allows two clocking options, either seif-
clocking (via an external resistor and capacitor) for stand-
alone applications, or for tighter cutoff frequency control an
external TTL or CMOS logic compatible clock can be ap-
plied. The maximally flat passband frequent response to-
gether with a DC gain of 1 WV allows cascading MF4 sec-
tions together for higher order filtering.
Features
" Low Cost
u Easy to use
a 8-pin mini-DIP or 14-pin wide-body S.O.
II No external components
I: 5V to 14V supply voltage
I: Cutoff frequency range of 0.1 Hz to 20 kHz
II Cutoff frequency accuracy of 1 0.3% typical
" Cutoff frequency set by external clock
tt Separate TTL and CMOtVSchmitrtrigger ciock inputs
Block and Connection Diagrams
FILTER
Dual-in-Line Package
tut "-i , , - "
L.8h-' s)--aan,
CuN-It
I 4m anoen
mi: " summm
Lamas mm
ta" ts "
WN-OVEHLAP‘HNE A
"L, 'r-Ill',"
TLfH/6064-2
Order Number MchN-so
or MchN-mo
1 See NS Package Number NDBE
Am Cl '
cm 1 sum»:
ti::r)ii:ye-rhsi't'k1'i.C_ut.-
CLOCK GENERITBI -
SmalI-Outllne
Wlde-Body Package
CLK IN -
CLK R -
14 ~11me
IS-tlt;
12 ,-stt
CLK ll L. "
10 -AGND
9 |-NC
- FILTER OUT
NmUI-FOIN‘
TL/H/5064-1
TL/HI5064-25
Top View
Order Number MF4CWM-50
or MF4CWM-1oo
See NS Package Number M143
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace apetrltled devlces are required,
please contact the National Semiconductor Sales
Offktemitttributortt for availability and specifications.
Supply Voltage (V + -N-) 14V
Voltage At Any Pin v+ + 0.2V
V' - 0.2V
Input Current at Any Pin (Note 14) 5 mA
Package Input Current (Note 14) 20 mA
Power Dissipation (Note 15) 500 mW
Storage Temperature 150°C
ESD Susceptibility (Note 13) 800 V
Soldering Information:
0 N Package: 10590. 260°C
. SO Package: Vapor Phase (60 sec.) 215''C
Infrared (15 sec.) 220°C
See AN-450 "Surface Mounting Methods and Their Effect
on Product Reliability" for other methods of soldering sur-
face mount devices.
Operating Ratings (Note 2)
Temperature Range Tmin 3 TA s: Tmax
MF4CN-50. MF4CN-100 0°C s; TA s 70''C
MF4CWM-50, MF4CWM-100 0'C 3 TA s; 70°C
Supply Voltage N + -v-o 5V to 14V
Filter Electrical Characteristics The following specifications apply for ‘CLK g 250 kHz (see Note 5) unless
otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = Tu = 25°C.
MF4-50 MF4-100
Parameter Conditions Tested Design Tested Deslgn Unit
Typical . Typical '
(Note IO) Llmlt Llmit (Note IO) Umit Limit
(Note 11) (Note 12) (Note It) (Note 12)
V+ = +w,v- = --5Y
fc, Cutoff Frequency Min 0.1 0.1 Hz
Range (Note 3) Max 20k 10k
Supply Current 'ch = 250 kHz 2.5 3.5 3.5 2.5 3.5 3.5 mA
Maximum Clock Filter Output Vin = 0V
Feedthrough 25 25 mV
(Peak-to-Peak)
Ho, DC Gain Rsource s 2 kn 0.0 $0.15 10.15 0.0 i015 to." dB
fclk/fc, Clock to Cutoff 49.96 49.96 49.98 99.09 99.09 99.09
Frequency Ratio 1- 0.3% , 0.8% i 0.6% i 0.3% t 1.0% i 0.6%
fclk/fc Temperature + + .
Coefficient _ 15 - 30 ppm/ C
Stopband Attenuation (Min) at 2 fc - 25.0 - 24.0 - 24.0 - 25.0 - 24.0 - 24.0 dB
DC Offset Voltage - 200 - 400 mV
Minimum Output Swing RL = 10 kn + 4.0 + 3.5 + 3.5 + 4.0 + 3.5 + " V
-4.5 -4.0 --a.o -4.5 -4.0 -4.0 V
Output Short Circuit Source 50 50 mA
Current (Note 8) Sink 1.5 1.5 mA
Dynamic Range (Note 4) 80 82 dB
Additional Magnitude f = 6000 Hz -7.57 - 7.57
Response Test Points k 0.27 i 0.27
N t 6 dB
( "fl ) 1=4500Hz -1.44 -N.qq
fclk - 250 kHz i 0.12 t 0.1 2
f = 3000 Hz - 7.21 -- 7.2 1
- 0.2 i o 2 dB
f = 2250 Hz -1.39 - 1.39
i 0.1 i: O. ,
Filter Electrical Characteristics The following specifications apply for fax s; 250 kHz (see Note 5) unless
otherwise specified. Boldface llmm apply for Tum to me; all other limits TA = Tu = 25°C. (Continued)
MF4-50 MF4-100
Parameter Conditions Typical Tested Deslgn Typical Tested Design Unit
(Note 10) lel1 Uttth (Note 10) Limit lelt
(Note 11) Mote 12) (Note 11) (Note 12)
V+ = + 2.5V, v- = -2.W
fc Cutoff Frequency min 0.1 0.1 Hz
Range (Note 3) max 10k 5k
Supply Current fclk = 250 kHz 1.5 2.25 2.25 1.5 2.25 2.25 mA
Maximum Clock
Feedthrough Filter Output Vin = OV 15 15 mV
(Peak-to-Peak)
Ho, DC Gain Rsource s; 2 kn 0.0 t 0.15 i 0.1 5 0.0 t 0.15 l o. 1 5 dB
fdk/fc, Clock to Cutoff 50.07 50.07 50.07 99.16 99.16 99.16
Frequency Ratio t 0.3% , 1.0% i 0.6% l 0.3% i 1.0% i 0.6%
icLK/fc Temperature "
Coefficient :25 160 ppm/ C
Stopband Attenuation (Min) at 2 fe - 25.0 -24.0 - 24.0 -25.0 -24.0 - 24.0 dB
DC Offset Voltage - 150 - 300 mV
Minimum Output Swing RL = 10 kn +1.5 + 1.0 + 1.0 +1.5 +1.0 + 1.0 V
-2.2 --1.7 - 1.7 -2.2 - 1.7 _ 1.7 V
Output Short Circuit Source 28 28 mA
Current (Note 8) Sink 0.5 0.5 mA
Dynamic Range (Note 4) 78 78 dB
Additional Magnitude talk = 250 kHz
Response Test Points
(Note 6) --7S7 - 7.57 dB
(fc = ti kHz) f = 6000 Hz i027 i 0.27
Magnitude at f = 4500 Hz - 1.46 - 1.45 dB
* 0.1 2 i o. 1 2
(fe = 2.5 kHz) == 3000 Hz -7.21 -7.21
Magnitude i 0.2 i 0.2 dB
- - 1.39 - 1 .39
f=2250Hz $0.1 i0”
Logic lnput-Output Characteristics The following specifications apply for V‘ = 0V (see Note 7) unless
otherwise sptmified. Boldface llmlta apply for Tum to Tox; all other limits TA = TJ = 25'G.
T lcal Tested Design
Parameter Cttetdltlttrttt JJ'l: 10) Limit leIt um
(Note 11) (Note 12)
SCHMITT TRIGGER
VT+, Positive Going Threshold Min V+ = 10V 7.0 6.1 6.1 V
Voltage Max 8.9
Min V+ == 5V 3.1 SA
Max 3.5 4.4 4.4 V
Logic input-Output Characteristics The following specifications applytorV- == 0V (see Note 7) unless
otherwise specified. Boldface llmlts apply for Tum to TMAX; all other limits TA = t, = 25°C. (Continued)
Typical Tested Design
Parameter Conditions (Note 10) Umlt lelt Unit
(Note 11) (Note 12)
SCHMITI' TRIGGER (Continued)
VT--, Negative Going Threshold Min v+ = 10V 3.0 1.3 ca V
Voltage Max 3.8 3.8
:22; W = 5V 1.5 'd 'e,' V
Hysteresis (VT+ -VT_) Min V+ = 10V 4.0 2.3 2.3 V
Max 7.6 7.6
iii; W =5V 2.0 $12 li', V
Minimum Logieal"1"OutputVoltagts lo = -10 pA V+ = 10V 9.0 9.0 V
(pin 2) v+ = 5V 4.5 4.5 v
Maximum Logical "ty' OutputVoltage Io = 10 pA v+ = 10V 1.0 1.0 V
(pin 2) v+ = 5V 0.5 0.5 v
Minimum Output Source Current CLK R Shorted V+ = 10V 6.0 3.0 a.o mA
(pin 2) to Ground v+ = 5V 1.5 0.75 o." mA
Maximum Output Sink Current CLK R Shorted v+ = 10V 5.0 2.5 2.5 mA
(pin i?) to W v+ = 5V 1.3 th65 0.65 tttA
TTL CLOCK INPUT, CLK R PIN (Note 9)
Maximum VIL: Logical "0" Input Voltage 0.8
Minimum VIH. Logical "I '' Input Voltage 2.0 V
Maximum Leakage Current at CLK R Pin L. Sh Pin at Mid-Supply 2.0 p.A
Note r. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. AC and DC electrical spscificattms do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are with respect to GND.
Note & The cutoff frequency of the filter is defined " the frequency where the magnitude response is 3.01 dB less than the Dc gain of the filter.
Note 4: For t 5V supplies the dynamic range is referenced to 2.82 Vrms (4V peak) where the wideband noise over a 20 kHz bandwidth is typically 280 meIs for
the MF4-50 and 230 erms tor the MF4-100. For 1 2.5V supplies the dynamic range is referenced to 1.08 Vrms (1.5V peak) where the widebend noise over a 20
kHz bandwidth is typically 130 erms for both the MF4-50 and the MF4-100.
Note 5: The tspecifications tor the MF4 have been given for a clock frequency (few) of 250 kHz or less. Above the clock frequency the cutoff frequency begins to
deviate from the specified error band of t0.6% but the filter still maintains its magnitude characteristics. See Application Hints.
Note tk Besides checking the cutoff frequency (tcl and the stopband attenuation at 2 to, two additional frequencies are used to check the magnitude response of
the filter. The magnitudes are referenced to a DC gain of 0.0 dB.
Note 7: For simplicity all the logic levels have been referenced to - = 0V (except for the TTL input Iog'c levels). The logic levels will scale accordingly for l 5V
and t2.5V suppliers.
Note 8: The shod circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to
the negative supply. The short circuit sink current is measured by lorclng the output that is being tested to its maximum negative voltage and then shorting that
output to the positive supply. These are worst case conditions.
Note 9: The MF4 is operating with symmetrical split supplies and L, Sh is tied to ground.
Note Ith Typicals are at 25‘C and represent most likely parametric norm.
Note 11: Guaranteed to National's Average Outgoing Quality Level (AOOL).
Note 12: Guaranteed, but not 100% prediction tested. These limits are not used to determine outgoing quality levels.
Note 13: Human body model; 100 pF discharged through a 1.5 kn resistor.
Note " When the input voltage MN) at any pin exceeds the power supply rails (VIN < " or VIN > V+)the absolute value of cument at that pin should be limited
to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA current limit to tour.
Note 15: Thermal Resistance
ggA (Junction to Ambient) N Package ........... 105'C/W.
OJA M Package ............................... 95'CIW.
7:!!!“
Typical Performance Characteristics
POSITIVE VOLTAGE SWING (V) POWER SUPPLY WRRENT (MA)
NEGATWE VOLTAGE swmcm
X CHANGE
Power Supply Current
vs Power Supply Voltage
rm = 250
§§Efl§6
25 M M M " M M m " "
POWER SUPPLY VOLTAGE (t V)
Positive Voltage Swing
vs Power Supply Voltage
Ta = 25°
'ax = 250 kHz
am”, = 10 m
2diM3diM4aM85M6SM
POWER SUPPLY vomsqzv)
Negative Voltage Swing
vs Temperature
-4.35 Fax = 25: kn
-55 -m 25 as 125
rwmrumx)
fcudfr, Deviation
vs Clock Frequency
100 500 1000
CLOCK FREQUENCY (kHz)
2 CHANGE NEGATIVE VOLTA6£ SWING (V) POWER SUPPLY CURRENTOM)
XCHANGE
Power Supply Current
vs Clock Frequency
1m an um
CLOCK razoumcmnz)
Negative Voltage Swing
vs Power Supply Voltage
Ft:ue2StutHz
" w M w a so M 5.0 " "
mm SUPPLY vomcu: v)
'CLKHO Devlatlon
tu vs Power Supply Voltage
" =t5Y
Fax = 250
NH- 100
" M M " " " " M M "
POWER SUPPLY VOLTAGE (t V)
ICLK/fc Deviation
vs Clock Frequency
VS =82.“
Vs =85.“
pNONa-aa
100 500 moo
CLOCK mzoummmz)
Pom SUPPtY CURRENI (MA)
POSITIVE VOLTAGE SWING”)
EEEEEE
X CHANGE
XCHANGE
ééééégseg
Power Supply Current
" Temperature
vs =:5.ov
§§33§B§§§8fi
Mili -15 a 85 15
TEMPERATURE te)
Posltlve Voltage Swing
vs Temperature
rm=2somz
-55 -1s 25 as 125
mpmrunz(°c)
'CLK/fc Devlatlon
B vs Power Supply Voltage
TA -- ae
rm: 250m
IIF4- 50
MM M m " an " M " "
POWER SUPPLY VOLTAGE (t v)
tcutffe Deviation
" Temperature
NFA-IOO
Fcu--2s0kitr Its"
V =22.5V
-55 ‘15 5 5 125
murawun: (e)
TLtH/5064-9
Typleal Performance Characteristlcs (Continued)
fcudto Dovlallon " Gnln Dovlatlon Dc Gain Dovlatlon
" Tomporaturo " Powor Supply Voltage " Power Supply Voltage
0.3 JU ts I 25 '0 0.04 TA = 25 'e
cm ''"yg', 'M-ZSOka om m2 a MO kHz
m m- too IT on m- so
on " - om
g.” g o
v tt.W -om
" -oz " , -om
MM il 4m
MM MIN
4.5 m -o.os
~55 -15 2: as 12: 2SM3SM4SMMMMM MMMM4SMMMMM
mmmn:(°c) pom sumv vows: (a v) POWER sumv vomc: (u)
06 Gain Deviation Dc Galn Deviatlon
" Temperature " Temperature
A -om . . A (MO
tl, Its "1-" , ln- 100
"ON MB (Mazsoknz
a -o.os , um
it M a
-o.1 -0.02
-55 -15 25 as 125 -55 35 125
TEMPERATURE te) mmmn: (°c)
TL/H/5064-10
Pin Descriptions
(Numbers in ( ) are for 14-pin package.)
Pln Pln
f Name
1 CLK IN A CMOS Schmitt-trigger input to be used
(1) with an external CMOS logic level clock.
Also used for self clocking Schmitt-trigger
oscillator (see section 1.1).
A TTL logic level clock input when in split
supply operation (i 2.5V to f 7V) with L. Sh
tied to system ground. This pin becomes a
low impedance output when L, Sh is tied to
V-. Also used in conjunction with the CLK
IN pin for a setf clocking Schmitt-trigger
oscillator (see section 1.1). The TTL input
signal must not exceed the supply voltages
by more than 0.2V.
Level shift pin; selects the logic threshoid
levels for the clock. When tied to v- it
enables an internal tri-state buffer stage
between the Schmitt trigger and the internal
clock level shift stage thus enabling the
CLK IN Schmitt-trigger input and making the
CLK R pin a low impedance output When
the voltage level at this input exceeds 25%
(V + - V-) + v- the internal tri-state
butter is disabled allowing the CLK R pin to
become the clock input for the internal
ciock leveI-shitt stage. The CLK R threshold
level is now 2v above the voltage on the L.
Sh pin. The CLK R pin will be compatible
with ITL logic levels when the MF4 is
operated on split supplies with the L. Sh pin
connected to system ground,
5 FILTER The output of the Iow-pass filter. it will
Function
2 CLK Ft
3 L. Sh
(8) OUT typically sink 0.9 mA and source 3 mA and
swing to within 1V of each supply rail.
6 AGND The analog ground pin. This pin sets the DC
(10) bias level for the filter section and must be
tied to the system ground for split supply
operation or to mid-supply for single supply
operation (see section 1.2). When tied to
mid-supply this pin should be well
bypassed.
T, 4 V+, v- The positive and negative supply pins. The
(7, 12) total power supply range is 5V to 14V.
Decoupling these pins with 0.1 pF
capacitors is highly recommended.
8 FILTER The input to the Iow-pass filter. To minimize
(14) N gain errors the source impedance that
drives this input should be less than 2K (see
section 1.3 of the Application Hints). For
single supply operation the input signal
must be biased to mid-supply or AC coupled
through a capacitor.
1.0 MF4 Application Hints
The MF4 is a non-inverting unity gain Iow-pass fourth-order
Butterworth meittthed-trapatritor filter. The switched-capaci-
tor topology makes the cutoff frequency (where the gain
drops 3.01 dB below the DC gain) a direct ratio (100:1 or
50:1) of the clock frequency supplied to the filter. Internal
integrator time constants set the filtar's cutoff frequency.
The resistive element of these integrators is actually tt ca-
pacitor which is "switched" at the clock frequency (for a
detailed discussion see Input Impedance Section). Varying
the clock frequency changes the value of this resistive ele-
ment and thus the time constant of the integrators. The
clock-to-cutoft-frequency ratio (fCLKfc) is set by the ratio of
the input and feedback capacitors in the integrators. The
higher the clock-to-cutoff-frequency ratio the closer this ap-
proximation is to the theoretical Butterworth response. The
MF4 is available in icLK/fc ratios of 50:1 (MF4-50) or 100:1
(MF4-100).
1.1 CLOCK INPUTS
The MF4 has a Schmitt-trigger inverting buffer which can be
used to construct a simple R/C oscillator. Pin 3 is connect-
ed to v- which makes Pin 2 a low impedance output. The
oscillator's frequency is nominally
fCLK = RCln [(VCC - VT_) (te' )]
Vcc - VT+ V
which, is typically
fcck E 1.69 RC ( )
torvcc = 10V. '
Note that tCLK is dependent on the buffer's threshold levels
as well as the resistor/capacitor tolerance (see Figure 1).
Schmitt-trigger threshold voltage levels can change signifi-
cantly causing the R/ C oscillator's frequency to vary greatly
from part to part.
Where accurate cutoff frequency is required, an external
clock can be used to drive the CLK Ft input of the MF4. This
input is TTL logic level compatible and also presents a very
light load to the external clock source (~2 pA). With split
supplies and the level shift (L. Sh) tied to system ground,
the logic level is about 2V. (See the Pin Description for L.
1.2 POWER SUPPLY
The MF4 can be powered from a single supply or split sup-
plies. The split supply mode shown in Figure 2 is the most
flexible and easiest to implement. Supply voltages of iSV
to 17V enable the use of TTL or CMOS clock logic leveis.
Figure 3 shows AGND resistor-biased to V+/2 tor single
supply operation. In this mode only CMOS clock logic levels
can be used, and input signals should be capacitor-coupled
or biased near mid-supply.
1.3 INPUT IMPEDANCE
The MF4 Iow-pass filter input (FILTER IN) is not a high im.
pedance buffer input. This input is a switched-capacitor re-
sistor equivalent, and its effective impedance is inversely
proportional to the clock frequency. The equivalent circuit of
the fiiter's input can be seen in Figure 4. The input capacitor
charges to Vin during the first halt of the clock period; during
the second half the charge is transferred to the feedback
capacitor. The total transfer of charge in one clock cycle is
therefore Q = cinvin. and since current is defined as the
flow of charge per unit time, the average input current be-
lin = 0/1
1.0 MF4 Application Hints (Continued)
(where T equals one clock period) or
ty, Vi
lin = Ill'-'-',-'!'-' = CinVin'CLK
The equivalent input resistor (Rin) then can be expressed as
Rin = _in =
lin CinfCLK
The input capacitor is 2 pF for the MF4-50 and 1 pF for the
MF4-100, so for the MF4-100
_1x1012_1x1012_1x1010
fCLK ch 100 fc
H._5x1011_5><1011_1><1010
In fCLK to x 50 fe
tor the MF4-50. The above equation shows that for a given
cutoff frequency (to). the input resistance of the MF4-5O is
the same as that of the MF4-100. The higher the clock-to-
cutoft-frequency ratio, the greater equivalent input resist-
ance tor a given clock frequency.
This input resistance will form a voltage divider with the
source impedance (Rsouree). Since Rin is inversely propor-
tional to the cutoff frequency. operation at higher cutoff tre-
quencies will be more likely to load the input signal which
would appear as an overall decrease in gain to the output of
the fitter. Since the filter's ideal gain is unity, the overall gain
is given by:
Rin + Ftsource
If the MF4-50 or the MF-100 were set up for a cutoff fre-
quency of 10 kHz the input impedance would be:
1 x 1010
Rin - 10 kHz
In this example with a source impedance of 10K the overall
gain, if the MF4 had an ideal gain of 1 or 0 dB, would be:
_ 1 Mn
- 10 m + 1 Mn
Since the maximum overall gain error for the MF4 is
:0.15 dB with Rs S 2 kn the actual gain error for this case
would be +0.06 dB to -0.24 dB.
1.4 CUTOFF FREQUENCY RANGE
The filter's cutoff frequency (fc) has a lower limit due to
leakage currents through the internal switches draining the
charge stored on the capacitors. At lower clock frequencies
these leakage currents can cause millivolts of error, for ex-
ample:
fCLK = 100 Hz, Ileakage = 1 PA, C = 1 pF
_ 1 pA
1 pF (100 Hz)
The propagation delay in the logic and the settling time re-
quired to acquire a new voltage level on the capacitors limit
the filter's accuracy at high clock frequencies. The ampli-
tude characteristic on iSV supplies will typically stay flat
until tCLK exceeds 750 kHz and then peak at about 0.5 dB
at the corner frequency with a 1 MHz clock. As supply volt-
age drops to d: 2.5V, a shift in the fCLK/fc ratio occurs
---1Mft
AV = 0.99009 or -0.086 dB
which will become noticeable when the clock frequency ex-
ceeds 250 kHz. The response of the MF4 is still a good
approximation of the ideal Butterworth low-pass characteris-
tic shown in Figure 5.
2.0 Designing With The MF4
Given any Iow-pass filter specification, two equations will
come in handy in trying to determine whether the MF4 will
do the job. The first equation determines the order of the
low-pass filter required to meet a given response specifica-
n - log [(100-1Amin - 1)/(100AAmax - 1)] (2)
2 log (is/tb)
where n is the order of the filter, Amin is the minimum stop-
band attenuation (in dB) desired at frequency ts, and Amax is
the passband ripple or attenuation (in dB) at cutoff frequen-
cy tb. If the result of this equation is greater than 4, more
than a single MF4 is required.
The attenuation at any frequency can be found by the tol.
lowing equation:
Attn (f) = 10log " ' (100-1Amax - 1) (f/tb)2“] dB (3)
where n = 4 for the MF4.
2.1 A LOW-PASS DESIGN EXAMPLE
Suppose the amplitude response specification in Figisre 6 is
given. Can the MF4 be used? The order of the Butterworth
approximation will have to be determined using (1):
Amin = 18 dB, Amax = 1.0 dB, ts = 2 kHz, and ft, = 1 kHz
n - log {(1018 - 1)/i100n - 1)]
2log(2)
Since n can only take on integer values, n = 4. Therefore
the MF4 can be used. In general, if n is 4 or less a single
MF4 stage can be utilized.
Likewise, the attenuation at is can be found using (3) with
the above values and n = 4:
Attn (2 kHz) = 10Iog il + 100-1 - 1) (2 kHz/1 kHz)3] '
18.28 dB
This result also meets the design specification given in Fig-
ure 6 again verifying that a single MF4 section will be ade-
quate.
Since the MF4's cutoff frequency (to). which corresponds to
a gain attenuation of -3.01 dB, was not specified in this
example, it needs to be calculated. Solving equation 3
wheret = to as follows:
f, _ (100-1(3-01 dB) - 1 1/(2n)
' b (100-1Amax - 1)
100-301 - l?"
100.1 - 1
1.184 kHz
where 16 = fCLK/SO or fCLK/100. To implement this exam-
ple for the MF4-50 the clock frequency will have to be set to
1cm = 50(1.1a4 kHz) = 59.2 kHz, or for the MF4-100. fcck
= 100 (1.184 kHz) = 118.4 kHz.
2.2 CASCADING MF4s
When a steeper stopband attenuation rate is required, two
MF4s can be cascaded (Figure 7) yielding an 8th order
= 3.95
=1kHz[
2.0 Deslgnlng With The MF4 (Continued)
slope of 48 dB per octave. Because the MF4 la a Butter.
worth filter and therefore has no ripple in Its passband when
MF4a are cascaded. the resulting tilter also has no ripple In
its passband. Likewise the DC and passband gains will re-
main at WA]. The resulting response ls shown in Figure 9.
ln determining whether the cascaded MFds will yield a filter
that will meet a particular amplitude response specification.
" above, equations 3 and 4 can be used, shown below.
n - Iogli100.0SAmin - 1)/(10.°-°5Amax - 1)]
2 log (fa/fe) (2)
Attn(f) = 10 log [1 + (100.05Amax - 1) (f/te)21 dB (3)
where n = 4 (the order of each filter).
Equation 2 will determine whether the order of the filter is
adequate (n s; 4) while equation 3 can determine the actual
stopband attenuation and cutoff frequency (to) necessary to
obtain the desired frequency response. The design proce-
dure would be Identical to the one shown in section 2.0.
2.3 CHANGING CLOCK FREQUENCY
INSTANTANEOUSLY
The MF4 will respond favorably to an instantaneous change
in clock frequency. If the control signal in Figure 9 is low the
TRI-STATE
MF4-50 has a 100 kHz clock making ta = 2 kHz: when this
signal goes high the clock frequency changes to 50 kHz
yielding tc = 1 kHz. As the Figure Illustrates. the output
signal changes quickly and smoothly In response to a sud.
den change In clock frequency.
The step response of the MF4 in Figure ft? is dependent on
fe The MF4 responds as a classical tourth-order Butter-
wonh low-pass filter.
2.4 ALIASING CONSIDERATIONS
Aliasing effects have to be considered when Input signal
frequencies exceed halt the sampling rate. For the MF4 this
equals halt the clock frequency (fCLK). When the input sig-
nal contains a component at a frequency higher than half
the clock frequency tth.x/2, as in Figure "a, that compo-
nent will be "reflected" about fa.K/2 into the frequency
range below ta.x/2, as in Flgure 11b. If this component is
within the passband of the filter and of large enough ampli-
tude it can cause problems. Therefore. if frequency compo-
nents in the input signal exceed ICLKZ they must be attenu-
ated before being applied to the MF4 Input. The necessary
amount of attenuation will vary depending on system re-
quirements. In critical applications the signal components
above ftxK/2 will have to be attenuated at least to the fit-
ter's residual noise level.
TL/H/5084-11
FIGURE 1. Schmltt Trigger n/c Oscillator
HN l I'
cut N mm: IN - cut IN FILTER M 3
l cut R f 7 5Y I I I I 2 7
-tr. IN - CLK tt v‘ Tm!
0.1 pr
3 'l" s 3 “n s 0.1 pr
.LSH m I,,.-,,,,'.-"""" LSh m _I
4 5 = - 0.1 HF -.
-5v y" FILTER our - - -sv I 4 y" mm cm JI -
Ihr, 2 0.8 Vec I " TL/H/5064-13
" S 0.2 vac =
Vee = " - v- TL/H/5064-12
(a) (b)
FIGURE 2. Split Supply Operation with CMOS Level Clock (a) and TTL Level Clock (b)
"W JIfL.
ov l CLK IN FILTER IN
3- cut R f
3 L.SH AGND
V' FILTER OUT
"Ir.' TL/H/5084-14
FIGURE 3. Slngle Supply Operation. ANGD Raslstm Biased to V+ "
NON - OVERLAPPING I l
CLOCKS
J, t, ll
FILTER
INPUT .--- FILTER
Rm INPUTS
cm y-----
'AGND tl _..-.!...,
', m - Cm ku; t
TL/H/5064-15 I AGND
TLfHM064-20
a) Equlvalont Circuit for MF4 Filter Input
FIGURE 4. MF4 Filter Input
b) Actual Clrcult for MF4 Filter Input
-IO t,
40 - , -
g -50 g l, ta l,. t5 g
10 100 um mmo 50.000 to 100 10.00 10.000 50.000 10 too moo am 50.00:)
mama (H1) nemutncv (Hz) mzoumcv (Hz)
FIGURE Stt. MF4-100 Amplitude FIGURE 5b. MF4-50 Amplitude FIGURE tith MF4M00 Amplitude
Response with i 5V Supplies Response with t 5V Supplies Response with , 2.5V Supplies
10 mo moo mm 50.000
moumcr (H1)
TL/H/5064-21
FIGURE 5d. MF4-50 Amplitude
Response with 1 2.5V Supplies
llllllllllll,
AMPLiiUDE (d8)
Ai.lm=-1a -----_---e---------
fb=1kHz fpz2kth
FREQUENCY (Hz)
TLlH/5064-22
FIGURE 6. Design Example Magnitude Response Speelmratlon where the Response of
the Filter Design must fall within the shaded area of the 'tpetgftttatlon
Di rm -'-l H F' um .2-Cl
FILTER AGND LSH v’ y" cut R FILTER FILTER AGND LSH f y" CLK R FILTER
IN 6 3 7 4 2 OUT IN 6 3 7 4 2 OUT
tht pf 0.1 “F
v‘ = +sv c T At
o.1 pF l 0.1 pr
v‘=-5vc T T
few C "i
TlV5064-23
FIGURE 7. Cascading Two MFds
lg: 20 kHz
10 100 woo soon o I 2 5 4
FREQUENCY (Hz) FREQUENCY (kHz)
TL/H/5064-18
FIGURE On. One MF4-50 FIGURE 8b. Phase Response
" Two MF4-508 Cascaded or Two Cascaded MF4-503
Vat l 'r.
men J Itt.
' n a I Ft I IVMN
" m: =
I) {$3113.11 Ll l mum:
lllillaiNllllilllll',
sr. am: m
"I.. ' ' ' mm “W5
5 wb 1 midi!
, < = = m:
““1“" t..=2sonz tux-wowz
TL/H/5064-.24 TL/H15064-19
FIGURE 9. MF6-50 Abrupt Clock Frequency Change FIGURE IO. MF4-50 Input Step Response
AMPLITUDE
t_s E. + t
FREQUENCY
(a) Input signal spectrum
TL/H/5064-16
AMPLITUDE
ls. -t It, It. +1 ts
Fasoueucv
TL/H/5064-17
(b) Output signal spectrum. Note that the Input slgnal at
fef2 + {causes an output signal to appear at fc/2 - f.
FIGURE 11. The phenomenon ot aliasing In sampled-data systems. An Input signal whose
frequency ls greater than ono-halt the sampling frequency will cause an output to appear
at a frequency lower than one-half the sampling frequency. m the MF4, fs = fCLK.
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
MF4CN-100 - product/mf4cn-100?HQS=T|-nu|I-null-dscatalog-df-pf-nuII-wwe
MF4CWM-50 - product/mf4cwm-50?HQS=T|-nu||-nuII-dscataIog-df-pf-null-wwe
MF4CWM-100 - product/mf4cwm-100?HQS=T|-nu|I-null-dscatalog-df—pf—nuII-wwe
