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MCM67C618AFN7
64K x 18 Bit BurstRAM Synchronous Fast Static RAM
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Registered OutputsThe MCM67C618A is a 1,179,648 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 65,536 words
of 18 bits, fabricated with Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive registered output drivers onto a single monolithic circuit
for reduced parts count implementation of cache data RAM applications. Syn-
chronous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals
except output enable (G) are clock (K) controlled through positive–edge–
triggered noninverting registers.
This device contains output registers for pipeline operations. At the ris-
ing edge of K, the RAM provides the output data from the previous cycle.
Output enable (G) is asynchronous for maximum system design flexibil-
ity.
Burst can be initiated with either address status processor (ADSP) or ad-
dress status cache controller (ADSC) input pins. Subsequent burst ad-
dresses can be generated internally by the MCM67C618A (burst
sequence imitates that of the i486 and Pentium) and controlled by the burst
address advance (ADV) input pin. The following pages provide more de-
tailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge
of the clock (K) input. This feature eliminates complex off–chip write pulse
generation and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually write-
able bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls
DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory. See Figure 2 for applications information. Single 5 V ± 5% Power Supply Fast Access Time/Fast Cycle Time = 5 ns/100 MHz, 7 ns/80 MHz Byte Writeable via Dual Write Enables Internal Input Registers (Address, Data, Control) Output Registers for Pipelined Applications Internally Self–Timed Write Cycle ADSP, ADSC, and ADV Burst Control Pins Asynchronous Output Enable Controlled Three–State Outputs Common Data Inputs and Data Outputs 3.3 V I/O Compatible High Board Density 52–Lead PLCC Package
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
PIN ASSIGNMENTSDQ9
VCC
DQ8
DQ6
DQ7
VSS
DQ4
DQ5
DQ2
DQ3
VSS
VCC
DQ0
DQ1
VCC
VSS
VSS
VCC
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17A7E A8A9A10 ADVADSCADSP
A15A3A2
A13A14 A12 A0
All power supply and ground pins must be
connected for proper operation of the device.
Order this document
by MCM67C618A/D-
SEMICONDUCTOR TECHNICAL DATA
