MCM67A618FN12 ,64K x 18 Bit Asychronous/Latched Address Fast Static RAM**Order this documentSEMICONDUCTOR TECHNICAL DATAby MCM67A618/DMCM67A61864K x 18 Bit Asynchronous/L ..
MCM67B618AFN10 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAMMAXIMUM RATINGS (Voltages Referenced to V = 0 V)SSThis device contains circuitry to protect theRati ..
MCM67B618AFN12 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAMBLOCK DIAGRAM (See Note)ADVBURST LOGICINTERNALADDRESSQ0A0′KA01664K × 18MEMORYQ1 A1′ARRAYCLR A1ADSCA ..
MCM67B618AFN9 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAMMAXIMUM RATINGS (Voltages Referenced to V = 0 V)SSThis device contains circuitry to protect theRati ..
MCM67B618AFN9 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAM**Order this documentSEMICONDUCTOR TECHNICAL DATAby MCM67B618A/DMCM67B618A64K x 18 Bit BurstRAMSyn ..
MCM67B618AFN-9 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAMBLOCK DIAGRAM (See Note)ADVBURST LOGICINTERNALADDRESSQ0A0′KA01664K × 18MEMORYQ1 A1′ARRAYCLR A1ADSCA ..
MIC2043-1BM , Single Channel, High Current, Low Voltage, Protected Power Distribution Switch
MIC2043-1BM , Single Channel, High Current, Low Voltage, Protected Power Distribution Switch
MIC2043-1BM , Single Channel, High Current, Low Voltage, Protected Power Distribution Switch
MIC2043-1BTS , Single Channel, High Current, Low Voltage, Protected Power Distribution Switch
MIC2043-1BTS , Single Channel, High Current, Low Voltage, Protected Power Distribution Switch
MIC2043-1YM , Single Channel, High Current, Low Voltage, Protected Power Distribution Switch
MCM67A618FN12
64K x 18 Bit Asychronous/Latched Address Fast Static RAM
64K x 18 Bit Asynchronous/
Latched Address Fast Static RAMThe MCM67A618 is a 1,179,648 bit latched address static random access
memory organized as 65,536 words of 18 bits, fabricated with Motorola’s high–
performance silicon–gate BiCMOS technology. The device integrates a 64K x 18
SRAM core with advanced peripheral circuitry consisting of address and data in-
put latches, active low chip enable, separate upper and lower byte write strobes,
and a fast output enable. This device has increased output drive capability sup-
ported by multiple power pins.
Address, data in, and chip enable latches are provided. When latch enables
(AL for address and chip enables and DL for data in) are high, the address, data
in, and chip enable latches are in the transparent state. If latch enables are tied
high the device can be used as an asynchronous SRAM. When latch enables are
low the address, data in, and chip enable latches are in the latched state. This
input latch simplifies read and write cycles by guaranteeing address and data–in
hold time in a simple fashion.
Dual write enables (LW and UW) are provided to allow individually writeable
bytes. LW controls DQ0 – DQ8 (the lower bits) while UW controls DQ9 – DQ17
(the upper bits).
Six pair of power and ground pins have been utilized and placed on the pack-
age for maximum performance.
The MCM67A618 will be available in a 52–pin plastic leaded chip carrier
(PLCC).
This device is ideally suited for systems that require wide data bus widths,
cache memory, and tag RAMs. Single 5 V ± 5% Power Supply Fast Access Times: 10/12/15 ns Max Byte Writeable via Dual Write Enables Separate Data Input Latch for Simplified Write Cycles Address and Chip Enable Input Latches Common Data Inputs and Data Outputs Output Enable Controlled Three–State Outputs 3.3 V I/O Compatible High Board Density 52–Lead PLCC Package
PIN ASSIGNMENTVCC
DQ10
DQ11
DQ12
DQ13
DQ14
VSS
VCC
DQ15
DQ16
DQ17
DQ7
DQ6
VCC
VSS
DQ5
DQ4
DQ3
DQ2
VSS
VCC
DQ1
DQ0
DQ8A3A2 A0
A15 A13A14 A12 A8A9A10GA6A7EUWL
