MCM62486BFN19 ,32K x 9 Bit BurstRAM Synchronous Static RAM**Order this documentSEMICONDUCTOR TECHNICAL DATAby MCM62486B/DMCM62486B32K x 9 Bit BurstRAMSynchr ..
MCM6249WJ20 ,1M x4 Bit Static Random Access Memory**Order this documentSEMICONDUCTOR TECHNICAL DATAby MCM6249/DMCM62491M x 4 Bit Static RandomAccess ..
MCM6264CJ12 ,8K x 8 Bit Fast Static RAMMAXIMUM RATINGS (See Note)This device contains circuitry to protect theRating Symbol Value Unitinpu ..
MCM6264CJ15 ,8K x 8 Bit Fast Static RAMBLOCK DIAGRAMA122 27 WA73 26 E2A2A64 25 A8VA3CCVA5SS 5 24 A9A4A4 A116 23A5MEMORY MATRIXA3 7 22GROW2 ..
MCM6264CJ15 ,8K x 8 Bit Fast Static RAM**Order this documentSEMICONDUCTOR TECHNICAL DATAby MCM6264C/DMCM6264C8K x 8 Bit Fast Static RAMThe ..
MCM6264CJ20 ,8K x 8 Bit Fast Static RAMMAXIMUM RATINGS (See Note)This device contains circuitry to protect theRating Symbol Value Unitinpu ..
MIC2005-1.2YML , Fixed and Adjustable Current Limiting Power Distribution Switches
MIC2005A-1YM6 , Fixed and Adjustable Current Limiting Power Distribution Switches
MIC2006-0.5YM6 , Fixed and Adjustable Current Limiting Power Distribution Switches
MIC2006-0.8YM6 , Fixed and Adjustable Current Limiting Power Distribution Switches
MIC2007YM6 , Fixed and Adjustable Current Limiting Power Distribution Switches
MIC2007YM6 , Fixed and Adjustable Current Limiting Power Distribution Switches
MCM62486BFN19
32K x 9 Bit BurstRAM Synchronous Static RAM
32K x 9 Bit BurstRAM
Synchronous Static RAM
With Burst Counter and Self–Timed WriteThe MCM62486B is a 294,912 bit synchronous static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 32,768 words of
9 bits, fabricated with Motorola’s high–performance silicon–gate CMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for re-
duced parts count implementation of cache data RAM applications. Synchro-
nous design allows precise cycle control with the use of an external clock (K).
CMOS circuitry reduces the overall power consumption of the integrated func-
tions for greater reliability.
Addresses (A0 – A14), data inputs (D0 – D8), and all control signals except
output enable (G) are clock (K) controlled through positive–edge–triggered
noninverting registers.
Bursts can be initiated with either address status processor (ADSP) or address
status cache controller (ADSC) input pins. Subsequent burst addresses can be
generated internally by the MCM62486B (burst sequence imitates that of the
i486 and Pentium) and controlled by the burst address advance (ADV) input pin.
The following pages provide more detailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
The MCM62486B will be available in a 44–pin plastic leaded chip carrier
(PLCC). Multiple power and ground pins have been utilized to minimize effects
induced by output noise. Separate power and ground pins have been employed
for DQ0 – DQ8 to allow user–controlled output levels of 5 volts or 3.3 volts. Single 5 V ± 10% Power Supply (± 5% for MCM62486BFN11) Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level
Compatibility Fast Access Times:11/12/14/19 ns Max and Cycle Times:15/20/25 ns Min Internal Input Registers (Address, Data, Control) Internally Self–Timed Write Cycle ADSP, ADSC, and ADV Burst Control Pins Asynchronous Output Enable Controlled Three–State Outputs Common Data Inputs and Data Outputs High Output Drive Capability: 85 pF per I/O High Board Density PLCC Package Fully TTL–Compatible Active High and Low Chip Select Inputs for Easy Depth Expansion
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.
