MC92500ZQ ,ATM Cell ProcessorFeatures• Full duplex operation at SONET STS-3c, SONET STS-1, DS3 PLCP, or any physical link runnin ..
MC92501GC ,ATM Cell ProcessorFeatures:¥ Full-Duplex Operation at Data Rates up to 155 Mbit/sec¥ Performs Internal VPI and VCI Ad ..
MC9328MX1VH20 , i.MX Integrated Portable System Processor
MC9328MX21CVK ,i.MX family of microprocessorsfeatures that can support a wide variety of applications. Below is a brief description of i.MX21
MC9328MX21DVG ,i.MX family of microprocessorsfeatures the advanced and power-efficient ARM926EJ-S core operating at speeds up to 266 MHz and is ..
MC9328MX21DVK ,i.MX family of microprocessorsMC9328MX21/DFreescale SemiconductorRev. 1.1, 09/29/2004Product PreviewMC9328MX21Package Information ..
MF-R050 , Almost anywhere there is a low voltage power supply and a load to be protected, including
MF-R160 , Almost anywhere there is a low voltage power supply and a load to be protected, including
MFRC500 01T ,The 鈥淥riginal鈥?MIFARE reader solutionGeneral descriptionThe MFRC500 is a highly integrated reader IC for contactless communication at 13 ..
MFRC500 01T ,The 鈥淥riginal鈥?MIFARE reader solutionFeatures and benefits3.1 General Highly integrated analog circuitry for demodulating and decoding ..
MFRC500 01T ,The 鈥淥riginal鈥?MIFARE reader solutionFeatures and benefits3.1 General Highly integrated analog circuitry for demodulating and decoding ..
MFRC50001T ,The 鈥淥riginal鈥?MIFARE reader solutionGeneral descriptionThe MFRC500 is a highly integrated reader IC for contactless communication at 13 ..
MC92500ZQ
ATM Cell Processor
The ATM Cell Processor (MC92500) is a peripheral device composed of dedicated
high performance Ingress and Egress Cell Processors combined with UTOPIA
Compliant PHY and Switch Interface ports (see Figure 1).
MC92500 Features Full duplex operation at SONET STS-3c, SONET STS-1, DS3 PLCP, or any physical link
running up to 155 Mbit/sec Implements ATM Layer functions for broadband ISDN according to ITU recommendations
and ATM forum UNI specification Performs internal VPI and VCI address compression (with an option for external
compression) for up to 64K VCs Supports up to 16 physical links using dedicated Ingress/Egress MultiPhy control signals Each physical link can be configured as either a UNI or NNI port Supports multicast, multiport address translation Maintains both virtual connection and physical link counters on both Ingress and Egress
cell flows for detailed billing and diagnostics Provides a flexible 32 bit external memory port for context management Automated AIS, RDI, CC and Loopback functions with Performance Monitoring Block Test
on up to 64 Bidirectional connections Programmable 32 bit microprocessor interface supporting either big- or little-endian bus
formats Per-connection leaky-bucket based UPC or NPC design with up to four buckets per
connection allows any combination of CLP-aware peak, average, and burst-length
policing with programmable tag/drop action per policer Implements separate rate controlled cell insertion and priority based cell extraction
queues accessible from all cell flows Supports a programmable number of additional switch overhead parameters allowing
