MC74VHCT373ADT ,Octal D-Type Latch with 3-State OutputMAXIMUM RATINGS*Symbol Parameter Value UnitThis device contains protectionÎÎÎcircuitry to guard aga ..
MC74VHCT373ADTR2 ,Octal Transparent Latch 3-StateON SemiconductorOctal D-Type LatchMC74VHCT373Awith 3-State OutputThe MC74VHCT373A is an advanced h ..
MC74VHCT373ADW ,Octal D-Type Latch with 3-State OutputELECTRICAL CHARACTERISTICSÎÎÎÎÎT = 25°C T = – 40 to 85°CA AÎÎV VCC CCVSb Symboll P Parameter T Test ..
MC74VHCT373AM ,Octal D-Type Latch with 3-State Output**SEMICONDUCTOR TECHNICAL DATA** * The MC74VHCT373A is an advanced high speed CMOS octal latch w ..
MC74VHCT373AMEL ,Octal D-Type Latch (TTL Compatible)**SEMICONDUCTOR TECHNICAL DATA** * The MC74VHCT373A is an advanced high speed CMOS octal latch w ..
MC74VHCT374ADTR2 ,Octal D-Type Flip-FlopELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)r fÎ T = 25°C T = – 40 to 85°CA AÎÎÎÎÎÎ MinÎÎÎ TypÎ ..
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MC74VHCT373ADT-MC74VHCT373ADW-MC74VHCT373AM
Octal D-Type Latch with 3-State Output
SEMICONDUCTOR TECHNICAL DATA- - -
The MC74VHCT373A is an advanced high speed CMOS octal latch with
3–state output fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
This 8–bit D–type latch is controlled by a latch enable input and an output
enable input. When the output enable input is high, the eight outputs are in a
high impedance state.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
The VHCT373A input and output (when disabled) structures provide
protection when voltages between 0V and 5.5V are applied, regardless of
the supply voltage. These input and output structures help prevent device
destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc. High Speed: tPD = 7.7ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5V to 5.5V Operating Range Low Noise: VOLP = 1.6V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 196 FETs or 49 Equivalent Gates
LOGIC DIAGRAMDATA
INPUTS18OE
NONINVERTING
OUTPUTSLE
FUNCTION TABLE
