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MC74VHCT139ADR2-MC74VHCT139ADTR2
Dual 2-to-4 Decoder/Demultiplexer
MC74VHCT139A
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Dual 2-to-4 Decoder/
Demultiplexer
The MC74VHCT139A is an advanced high speed CMOS 2−to−4
decoder/ demultiplexer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL devices while maintaining CMOS low power dissipation.
When the device is enabled (E = low), it can be used for gating or as a
data input for demultiplexing operations. When the enable input is held
high, all four outputs are fixed high, independent of other inputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device output is compatible with TTL−type input thresholds and
the output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic to 3.0 V
CMOS logic while operating at the high−voltage power supply
The MC74VHCT139A input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHCT139A to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage—input/output voltage mismatch, battery backup, hot
insertion, etc. High Speed: tPD = 5.0 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 4 �Α (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 2 V to 5.5 V Operating Range Low Noise: VOLP = 0.8 V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Chip Complexity: 100 FETs or 25 Equivalent Gates
Figure 1. Pin AssignmentA1a
A0a
GND
A1b
A0b
VCC
Y0a
Y1a
Y2a
Y3a
Y0b
Y1b
Y2b
Y3b
