MC74VHC1GT32DFT1 ,Single 2 Input OR Gate, TTL LevelMAXIMUM RATINGS (Note 1)Symbol Characteristics Value UnitV DC Supply Voltage –0.5 to +7.0 VCCV DC I ..
MC74VHC1GT32DFT2 ,Single 2 Input OR Gate, TTL LevelThe internal circuit is composed of three stages, including a bufferoutput which provides high nois ..
MC74VHC1GT32DTT1 ,Single 2 Input OR Gate, TTL LevelMaximum Ratings are those values beyond which damage to the device may occur. Exposure to these con ..
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MC74VHC1GT50DF ,Noninverting Buffer / CMOS Logic Level Shiftersimilar to equivalent Bipolar Schottky TTL while maintaining CMOSlow power dissipation.MARKINGThe i ..
MC74VHC1GT50DF2G ,Single Buffer Non Inverting, TTL Level
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MC74VHC1GT32-MC74VHC1GT32DF1G-MC74VHC1GT32DFT1-MC74VHC1GT32DFT2-MC74VHC1GT32DTT1
Single 2 Input OR Gate, TTL Level
MC74VHC1GT32
2-Input OR Gate/CMOS
Logic Level Shifter
The MC74VHC1GT32 is an advanced high speed CMOS 2–input OR
gate fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic–level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high–voltage power supply.
The MC74VHC1GT32 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT32 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage – input/output voltage mismatch, battery backup, hot
insertion, etc. High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 2 μA (Max) at TA = 25°C TTL–Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V CMOS–Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 65; Equivalent Gates = 15
Figure 1. Pinout (T op View)
VCCIN B
IN A
OUT YGND
IN A
IN B OUT Y
