MC74VHC1GT125DF1 ,Single Buffer Noninverting, TTL Levelsimilar to equivalent Bipolar Schottky TTL while maintaining CMOSlow power dissipation.MARKINGThe M ..
MC74VHC1GT125DF1G , Noninverting Buffer CMOS Logic Level Shifter
MC74VHC1GT125DF2 ,Single Buffer Noninverting, TTL LevelELECTRICAL CHARACTERISTICS Input t = t = 3.0 nsr fÎÎT = 25°C T ≤ 85°C −55 ≤ T ≤ 125°CA A AÎÎÎÎMin T ..
MC74VHC1GT125DT1 ,Single Buffer Noninverting, TTL LevelELECTRICAL CHARACTERISTICST = 25°C T ≤ 85°C −55 ≤ T ≤ 125°CÎÎÎÎÎ AÎÎÎÎ AÎÎÎÎÎÎ AÎÎV VCC CC(V) Min T ..
MC74VHC1GT126DF2 ,Single Buffer Non-Inverting, TTL LevelELECTRICAL CHARACTERISTICS Input t = t = 3.0 nsr fÎÎT = 25°C T ≤ 85°C −55 ≤ T ≤ 125°CA A AÎÎÎÎÎMin ..
MC74VHC1GT126DT1 ,Single Buffer Non-Inverting, TTL Leveloperation similar to equivalent Bipolar Schottky TTL while maintainingCMOS low power dissipation.MA ..
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MDT10P22A2K , 8-bit micro-controller
MC74VHC1GT125-MC74VHC1GT125DF1-MC74VHC1GT125DF2-MC74VHC1GT125DT1
Single Buffer Noninverting, TTL Level
MC74VHC1GT125
Noninverting Buffer /
CMOS Logic Level Shifter
with LSTTL−Compatible InputsThe MC74VHC1GT125 is a single gate noninverting buffer fabricated
with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS
low power dissipation.
The MC74VHC1GT125 requires the 3−state control input (OE) to be
set High to place the output into the high impedance state.
The device input is compatible with TTL−type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic−level translator from 3.0 V
CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high−voltage power supply.
The MC74VHC1GT125 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT125 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc. High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1 �A (Max) at TA = 25°C TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 62; Equivalent Gates = 16
Figure 1. Pinout (T op View)
IN A OUT Y
VCCOE
IN A
OUT YGND
Figure 2. Logic Symbol
