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MC74VHC1G125DFT1G-MC74VHC1G125DFT2G-MC74VHC1G125DTT1G Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
MC74VHC1G125DFT1GONN/a1872avaiNoninverting 3-State Buffer
MC74VHC1G125DFT2GONN/a264000avaiNoninverting 3-State Buffer
MC74VHC1G125DTT1GONN/a14850avaiNoninverting 3-State Buffer


MC74VHC1G125DFT2G ,Noninverting 3-State Buffer3MC74VHC1G125SWITCHING WAVEFORMSVCCOE50%V GNDCC50%t tPZL PLZAGND HIGHtt PHL IMPEDANCEPLH50% VY CCV ..
MC74VHC1G125DTT1 ,Single Non Inverting Buffer, 3-StateELECTRICAL CHARACTERISTICST = 25°C T ≤ 85°C −55 ≤ T ≤ 125°CA A AV VCC CC(V) Min Typ Max Min Max Min ..
MC74VHC1G125DTT1G ,Noninverting 3-State BufferELECTRICAL CHARACTERISTICST = 25°C T ≤ 85°C −55 ≤ T ≤ 125°CA A AV VCC CC(V) Min Typ Max Min Max Min ..
MC74VHC1G126 ,Single Non Inverting Buffer, 3-StateThe internal circuit is composed of three stages, including a buffered3−state output which provides ..
MC74VHC1G126DF1G ,Single Non Inverting Buffer, 3-State3MC74VHC1G126SWITCHING WAVEFORMSVCCOE50%V GNDCC50%t tPZL PLZAGND HIGHtt PHL IMPEDANCEPLH50% VY CCV ..
MC74VHC1G126DFT1 ,Single Non Inverting Buffer, 3-StateELECTRICAL CHARACTERISTICS C = 50 pF, Input t = t = 3.0 nsload r fÎÎÎÎÎT = 25°C T ≤ 85°C −55 ≤ T ≤ ..
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MC74VHC1G125DFT1G-MC74VHC1G125DFT2G-MC74VHC1G125DTT1G
Noninverting 3-State Buffer
MC74VHC1G125
Noninverting 3-State Buffer
The MC74VHC1G125 is an advanced high speed CMOS
noninverting 3−state buffer fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including a buffered
3−state output which provides high noise immunity and stable output.
The MC74VHC1G125 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G125 to be used to interface 5.0 V circuits to
3.0 V circuits.
Features
These are Pb−Free Devices High Speed: tPD = 3.5 ns (Typ) at VCC = 5.0 V Low Power Dissipation: ICC = 1 �A (Max) at TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 58; Equivalent Gates = 15
Figure 1. Pinout (T
op View)
VCCOE
IN A
OUT YGND
IN A OUT YOE
Figure 2. Logic Symbol
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