MC74LCX74DR2 ,Low-Voltage CMOS Dual D-Type Flip-FlopLogic DiagramPIN NAMESPins FunctionCP1, CP2 Clock Pulse InputsD1−D2 Data InputsCD1, CD2 Direct Clea ..
MC74LCX74DT ,Low-Voltage CMOS Dual D-Type Flip-FlopMaximum ratings applied to the device are individual stress limitvalues (not normal operating condi ..
MC74LCX74DTR2 ,Low-Voltage CMOS Dual D-Type Flip-FlopFeatures• Designed for 2.3 V to 3.6 V V OperationCCLCXTSSOP−14• 5 V Tolerant Inputs − Interface Cap ..
MC74LCX74MEL ,Low-Voltage CMOS Dual D-Type Flip-Flophttp://onsemi.comwith asynchronous clear and set inputs and complementary (O, O)outputs. It operate ..
MC74LCX74MEL ,Low-Voltage CMOS Dual D-Type Flip-FlopELECTRICAL CHARACTERISTICST = −40°C to +85°CASymbol Characteristic Condition Min Max UnitV HIGH Lev ..
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MC74LCX74DR2-MC74LCX74DT-MC74LCX74DTR2-MC74LCX74MEL
Low-Voltage CMOS Dual D-Type Flip-Flop
MC74LCX74
Low-Voltage CMOS Dual
D-Type Flip-Flop
With 5 V−Tolerant InputsThe MC74LCX74 is a high performance, dual D−type flip−flop
with asynchronous clear and set inputs and complementary (O, O)
outputs. It operates from a 2.3 to 3.6 V supply. High impedance TTL
compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5 V allows MC74LCX74 inputs
to be safely driven from 5 V devices.
The MC74LCX74 consists of 2 edge−triggered flip−flops with
individual D−type inputs. The flip−flop will store the state of
individual D inputs, that meet the setup and hold time requirements, on
the LOW−to−HIGH Clock (CP) transition.
Features Designed for 2.3 V to 3.6 V VCC Operation 5 V Tolerant Inputs − Interface Capability With 5 V TTL Logic LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 �A)
Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V
Machine Model >200 V Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
