MC74LCX74 ,Low-Voltage CMOS Dual D-Type Flip-Flop**SEMICONDUCTOR TECHNICAL DATA**!** * * ** "** * * * **The MC74LCX74 is a high performance, dual ..
MC74LCX74DR2 ,Low-Voltage CMOS Dual D-Type Flip-FlopLogic DiagramPIN NAMESPins FunctionCP1, CP2 Clock Pulse InputsD1−D2 Data InputsCD1, CD2 Direct Clea ..
MC74LCX74DT ,Low-Voltage CMOS Dual D-Type Flip-FlopMaximum ratings applied to the device are individual stress limitvalues (not normal operating condi ..
MC74LCX74DTR2 ,Low-Voltage CMOS Dual D-Type Flip-FlopFeatures• Designed for 2.3 V to 3.6 V V OperationCCLCXTSSOP−14• 5 V Tolerant Inputs − Interface Cap ..
MC74LCX74MEL ,Low-Voltage CMOS Dual D-Type Flip-Flophttp://onsemi.comwith asynchronous clear and set inputs and complementary (O, O)outputs. It operate ..
MC74LCX74MEL ,Low-Voltage CMOS Dual D-Type Flip-FlopELECTRICAL CHARACTERISTICST = −40°C to +85°CASymbol Characteristic Condition Min Max UnitV HIGH Lev ..
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MD82C37A-5/B ,CMOS High Performance Programmable DMA Controller82C37ACMOS High PerformanceMarch 1997 Programmable DMA Controller
MD82C50A/5/B ,CMOS Asynchronous Communications Element82C50ACMOS AsynchronousCommunications ElementMarch 1997
MD82C50A-5/B ,CMOS Asynchronous Communications Element82C50ACMOS AsynchronousCommunications ElementMarch 1997
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MD82C52/B ,CMOS Serial Controller InterfaceFeatures Description• Single Chip UART/BRG The Intersil 82C52 is a high performance programmableUni ..
MC74LCX74
LOW-VOLTAGE CMOS DUAL D-TYPE FLIP-FLOP
SEMICONDUCTOR TECHNICAL DATA -" --
The MC74LCX74 is a high performance, dual D–type flip–flop with
asynchronous clear and set inputs and complementary (O, O) outputs. It
operates from a 2.7 to 3.6V supply. High impedance TTL compatible
inputs significantly reduce current loading to input drivers while TTL
compatible outputs offer improved switching noise performance. A VI
specification of 5.5V allows MC74LCX74 inputs to be safely driven from
5V devices.
The MC74LCX74 consists of 2 edge–triggered flip–flops with
individual D–type inputs. The flip–flop will store the state of individual D
inputs, that meet the setup and hold time requirements, on the
LOW–to–HIGH Clock (CP) transition. Designed for 2.7 to 3.6V VCC Operation 5V T olerant Inputs — Interface Capability With 5V TTL Logic LVTTL Compatible LVCMOS Compatible 24mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10μA)
Substantially Reduces System Power Requirements Latchup Performance Exceeds 500mA ESD Performance: Human Body Model >2000V; Machine Model >200V
Pinout: 14–Lead (Top View)VCC CD2 D2 CP2 SD2O2 O2
CD1 D1 CP1 SD1O1 O1 GND
PIN NAMES
