MC74LCX573DTR2 ,Low-Voltage CMOS Octal Transparent Latch Flow Through PinoutMC74LCX573Low-Voltage CMOSOctal Transparent LatchFlow Through PinoutWith 5 V−Tolerant Inputs and Ou ..
MC74LCX573DTR2 ,Low-Voltage CMOS Octal Transparent Latch Flow Through PinoutLogic DiagramTRUTH TABLEINPUTS OUTPUTSOE LE Dn OnOPERATING MODEL H H HTransparent (Latch Disabled); ..
MC74LCX573DTR2 ,Low-Voltage CMOS Octal Transparent Latch Flow Through PinoutMAXIMUM RATINGSSymbol Parameter Value Condition UnitV DC Supply Voltage −0.5 to +7.0 VCCV DC Input ..
MC74LCX573DW ,Low-Voltage CMOS Octal Transparent Latch Flow Through PinoutFeatures74LCX573M SUFFIXAWLYWW• Designed for 2.3 to 3.6 V V OperationCC CASE 967201• 5V Tolerant − ..
MC74LCX573DW ,Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout**SEMICONDUCTOR TECHNICAL DATA*")**" & * **&* *$*!%#*$ * *!& **& ") **$"’** **!"’&**&* " *$*!& * *! ..
MC74LCX573DW ,Low-Voltage CMOS Octal Transparent Latch Flow Through PinoutMAXIMUM RATINGS*Symbol Parameter Value Condition UnitV DC Supply Voltage –0.5 to +7.0 VCCV DC Input ..
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MC74LCX573DT-MC74LCX573DTR2-MC74LCX573DW-MC74LCX573DWR2
Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout
MC74LCX573
Low-Voltage CMOS
Octal Transparent Latch
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)The MC74LCX573 is a high performance, non−inverting octal
transparent latch operating from a 2.3 to 3.6 V supply. High
impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX573 inputs to be safely driven from 5.0 V devices.
The MC74LCX573 contains 8 D−type latches with 3−state standard
outputs. When the Latch Enable (LE) input is HIGH, data on the Dn
inputs enters the latches. In this condition, the latches are transparent,
i.e., a latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was present
on the D inputs a setup time preceding the HIGH−to−LOW transition
of LE. The 3−state standard outputs are controlled by the Output
Enable (OE) input. When OE is LOW, the standard outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches. The LCX573 flow through design facilitates easy PC
board layout.
Features Designed for 2.3 to 3.6 V VCC Operation 5V Tolerant − Interface Capability With 5 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 �A)
Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V
Machine Model >200 V Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
