MC74LCX373DWR2 ,Low-Voltage CMOS Octal Transparent LatchFeatures• Designed for 2.3 to 3.6 V V OperationCC20• 5 V Tolerant − Interface Capability With 5 V T ..
MC74LCX373M ,Low Voltage CMOS Octal transparent Latch with 5V-Tolerant Inputs and Outputs (3-state, Non-Inverting)LOGIC DIAGRAM1OE11LE2nLE3 O0QD0 D5nLE4 O1QD1D6nLE7 O2QD2 D9nLE8 O3QD3 D12nLE13 O4QD4 D15nLE14 O5QD5 ..
MC74LCX374 ,LOW-VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOPThe MC74LCX374 is a high performance, non−inverting octalD−type flip−flop operating from a 2.3 to 3 ..
MC74LCX374DT ,LOW-VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP**SEMICONDUCTOR TECHNICAL DATA*")**" & * &* *#* * *#** "#**&* " *$*!& * *!#’&% *!* *’&#’&%*&*&** ..
MC74LCX374DT ,LOW-VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOPMAXIMUM RATINGS*Symbol Parameter Value Condition UnitV DC Supply Voltage –0.5 to +7.0 VCCV DC Input ..
MC74LCX374DTR2 ,Low-Voltage CMOS Octal D-Type Flip-FlopMaximum ratings applied to the device are individual stress limitvalues (not normal operating condi ..
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MC74LCX373DWR2
Low-Voltage CMOS Octal Transparent Latch
MC74LCX373
Low-Voltage CMOS
Octal Transparent Latch
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)The MC74LCX373 is a high performance, non−inverting octal
transparent latch operating from a 2.3 to 3.6 V supply. High
impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX373 inputs to be safely driven from 5 V devices.
The MC74LCX373 contains 8 D−type latches with 3−state outputs.
When the Latch Enable (LE) input is HIGH, data on the Dn inputs
enters the latches. In this condition, the latches are transparent, i.e., a
latch output will change state each time its D input changes. When LE
is LOW, the latches store the information that was present on the D
inputs a setup time preceding the HIGH−to−LOW transition of LE.
The 3−state standard outputs are controlled by the Output Enable (OE)
input. When OE is LOW, the standard outputs are enabled. When OE
is HIGH, the standard outputs are in the high impedance state, but this
does not interfere with new data entering into the latches.
Features Designed for 2.3 to 3.6 V VCC Operation 5 V Tolerant − Interface Capability With 5 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in all Three Logic States (10 �A)
Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V
Machine Model >200 V Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
