MC74LCX373M ,Low Voltage CMOS Octal transparent Latch with 5V-Tolerant Inputs and Outputs (3-state, Non-Inverting)LOGIC DIAGRAM1OE11LE2nLE3 O0QD0 D5nLE4 O1QD1D6nLE7 O2QD2 D9nLE8 O3QD3 D12nLE13 O4QD4 D15nLE14 O5QD5 ..
MC74LCX374 ,LOW-VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOPThe MC74LCX374 is a high performance, non−inverting octalD−type flip−flop operating from a 2.3 to 3 ..
MC74LCX374DT ,LOW-VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP**SEMICONDUCTOR TECHNICAL DATA*")**" & * &* *#* * *#** "#**&* " *$*!& * *!#’&% *!* *’&#’&%*&*&** ..
MC74LCX374DT ,LOW-VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOPMAXIMUM RATINGS*Symbol Parameter Value Condition UnitV DC Supply Voltage –0.5 to +7.0 VCCV DC Input ..
MC74LCX374DTR2 ,Low-Voltage CMOS Octal D-Type Flip-FlopMaximum ratings applied to the device are individual stress limitvalues (not normal operating condi ..
MC74LCX374DTR2G , Low-Voltage CMOS Octal D-Type Flip-Flop
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MD82C37A-5/B ,CMOS High Performance Programmable DMA Controller82C37ACMOS High PerformanceMarch 1997 Programmable DMA Controller
MC74LCX373DT-MC74LCX373DW-MC74LCX373M
LOW-VOLTAGE CMOS OCTAL TRANSPARENT LATCH
SEMICONDUCTOR TECHNICAL DATA ’ $ $"#!"$ $- "$ !%$# %$!%$#
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The MC74LCX373 is a high performance, non–inverting octal
transparent latch operating from a 2.7 to 3.6V supply. High impedance
TTL compatible inputs significantly reduce current loading to input drivers
while TTL compatible outputs offer improved switching noise
performance. A VI specification of 5.5V allows MC74LCX373 inputs to be
safely driven from 5V devices.
The MC74LCX373 contains 8 D–type latches with 3–state outputs.
When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters
the latches. In this condition, the latches are transparent, i.e., a latch
output will change state each time its D input changes. When LE is LOW,
the latches store the information that was present on the D inputs a setup
time preceding the HIGH–to–LOW transition of LE. The 3–state standard
outputs are controlled by the Output Enable (OE) input. When OE is
LOW, the standard outputs are enabled. When OE is HIGH, the standard
outputs are in the high impedance state, but this does not interfere with
new data entering into the latches. Designed for 2.7 to 3.6V VCC Operation 5V T olerant — Interface Capability With 5V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0V LVTTL Compatible LVCMOS Compatible 24mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10μA)
Substantially Reduces System Power Requirements Latchup Performance Exceeds 500mA ESD Performance: Human Body Model >2000V; Machine Model >200V
Pinout: 20–Lead (Top View)VCC D7 D6 O6 O5 D5 D4 O4 LE O0 D0 D1 O1 O2 D2 D3 O3 GND
PIN NAMES
