MC74LCX16373DTR2 ,Low-Voltage CMOS 16-Bit Transparent Latchelectrical characteristics only.IAC CHARACTERISTICS t = t = 2.5 ns; C = 50 pF; R = 500 R F L LT = ..
MC74LCX16373DTR2 ,Low-Voltage CMOS 16-Bit Transparent LatchFeaturesAWLYYWW• Designed for 2.3 to 3.6 V V OperationCC• 5.4 ns Maximum tpd1• 5 V Tolerant − Inter ..
MC74LCX16374 ,LOW-VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOPFeatures• Designed for 2.3 to 3.6 V V OperationCCLCX16374• 6.2 ns Maximum tAWLYYWWpd• 5 V Tolerant ..
MC74LCX16374DT ,Low-Voltage CMOS 16-Bit D-Type Flip-Flopelectrical characteristics only.IAC CHARACTERISTICS t = t = 2.5 ns; C = 50 pF; R = 500 R F L LT = ..
MC74LCX16374DTR2 ,Low-Voltage CMOS 16-Bit D-Type Flip-Flophttp://onsemi.comThe MC74LCX16374 is a high performance, non−inverting 16−bitD−type flip−flop opera ..
MC74LCX16374DTR2 ,Low-Voltage CMOS 16-Bit D-Type Flip-FlopELECTRICAL CHARACTERISTICST = −40°C to +85°CAMin MaxSymbol Characteristic Condition UnitV HIGH Leve ..
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MC74LCX16373-MC74LCX16373DTR2
Low-Voltage CMOS 16-Bit Transparent Latch
MC74LCX16373
Low-Voltage CMOS 16-Bit
Transparent Latch
With 5 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)The MC74LCX16373 is a high performance, non−inverting 16−bit
transparent latch operating from a 2.3 V to 3.6 V supply. The device is
byte controlled. Each byte has separate Output Enable and Latch Enable
inputs. These control pins can be tied together for full 16−bit operation.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
MC74LCX16373 inputs to be safely driven from 5 V devices.
The MC74LCX16373 contains 16 D−type latches with 3−state
5 V−tolerant outputs. When the Latch Enable (LEn) inputs are HIGH,
data on the Dn inputs enters the latches. In this condition, the latches are
transparent, i.e., a latch output will change state each time its D input
changes. When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the HIGH−to−LOW
transition of LE. The 3−state outputs are controlled by the Output
Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When
OE is HIGH, the standard outputs are in the high impedance state, but
this does not interfere with new data entering into the latches.
Features Designed for 2.3 to 3.6 V VCC Operation 5.4 ns Maximum tpd 5 V Tolerant − Interface Capability With 5 V TTL Logic Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V LVTTL Compatible LVCMOS Compatible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (20 �A)
Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 mA ESD Performance: Human Body Model >2000 V;
Machine Model >200 V All Devices in Package TSSOP are Inherently Pb−Free*
