MC74HCT541ADWR2 ,Octal 3-State Non Inverting Buffer/Line Driver3MC74HCT541APIN DESCRIPTIONSINPUTS outputs are enabled and the device functions as aA1, A2, A3, A4, ..
MC74HCT541AF ,Octal 3-State Non Inverting Buffer/Line Driver2MC74HCT541AAC CHARACTERISTICS (V = 5.0V, C = 50 pF, Input t = t = 6 ns)CC L r fGuaranteed LimitSym ..
MC74HCT541AFL1 ,Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver WIth LSTTL-Compatible Inputs2MC74HCT541AAC CHARACTERISTICS (V = 5.0V, C = 50 pF, Input t = t = 6 ns)CC L r fGuaranteed LimitSym ..
MC74HCT541AFL1 ,Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver WIth LSTTL-Compatible InputsMaximum Ratings are those values beyond which damage to the device may occur.Functional operation s ..
MC74HCT541AN ,Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver With LSTTL-Compatible Inputs
MC74HCT573ADT ,Octal 3-State NonInverting Transparent Latch with LSTTL Compatible Inputs
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MC74HCT541ADTR2-MC74HCT541ADW-MC74HCT541ADWR2-MC74HCT541AF
Octal 3-State Non Inverting Buffer/Line Driver
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High–Performance Silicon–Gate CMOSThe MC74HCT541A is identical in pinout to the LS541. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to high speed CMOS inputs.
The HCT541A is an octal non–inverting buffer/line driver/line
receiver designed to be used with 3–state memory address drivers,
clock drivers, and other bus–oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active–low output enables. Output Drive Capability: 15 LSTTL Loads TTL/NMOS–Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5V Low Input Current: 1μA In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 134 FETs or 33.5 Equivalent GatesY1A1Y2A2Y3A3Y4A4Y5A5Y6A6Y7A7Y8A8
OE1
OE2
Output
Enables
Data
Inputs
Non–Inverting
Outputs
PIN 20 = VCC
PIN 10 = GND
LOGIC DIAGRAM
Pinout: 20–Lead Packages (Top View)VCC
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
FUNCTION TABLEZ = High Impedance
X = Don’t Care
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MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
PDIP–20
N SUFFIX
CASE 738
ORDERING INFORMATION
