MC74HC74ADR2 ,Flip-Flop D-Type Type DualMaximum ratingsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎapplied to the device are individual stress limit values (not ..
MC74HC74ADR2G , Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
MC74HC74ADT ,Dual D Flip-Flop with Set and Reset
MC74HC74ADTR2 ,Flip-Flop D-Type Type DualFeatures1• Pb−Free Packages are Available**14• Output Drive Capability: 10 LSTTL LoadsSOIC−14HC74A• ..
MC74HC74AF ,Flip-Flop D-Type Type DualMC74HC74ADual D Flip-Flop with Setand ResetHigh−Performance Silicon−Gate CMOSThe MC74HC74A is ident ..
MC74HC74AFEL ,Flip-Flop D-Type Type DualMC74HC74ADual D Flip-Flop with Setand ResetHigh−Performance Silicon−Gate CMOSThe MC74HC74A is ident ..
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0007TR ,Low Cost MMIC Mixer, 2.1
MC74HC74A-MC74HC74AD-MC74HC74ADR2-MC74HC74ADTR2-MC74HC74AF-MC74HC74AFEL-MC74HC74AN
Flip-Flop D-Type Type Dual
MC74HC74A
Dual D Flip-Flop with Set
and Reset
High−Performance Silicon−Gate CMOSThe MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
Features Pb−Free Packages are Available** Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 �A High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. 7.0 A Requirements Chip Complexity: 128 FETs or 32 Equivalent Gates
RESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
Figure 1. LOGIC DIAGRAM
