MC74HC73D ,Dual J-K Flip-Flop with ResetLOGIC DIAGRAMRESET 1 2 13 Q1K1 3 12 Q114V 4 11 GNDCCJ112Q1CLOCK 2 5 10 K21CLOCK 1RESET 2 6 9 Q213Q1 ..
MC74HC73D- ,Dual J-K Flip-Flop with ResetELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)L r fÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC73N ,Dual J-K Flip-Flop with ResetMaximum Ratings are those values beyond which damage to the device may occur.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC74 ,Dual D Flip-Flop with Set and ResetLOGIC DIAGRAM11RESET 1 A = Assembly LocationWL or L = Wafer Lot52YY or Y = YearDATA 1Q1WW or W = Wo ..
MC74HC74 ,Dual D Flip-Flop with Set and ResetELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)L r fÎÎGuaranteed LimitÎÎÎÎÎÎV – 55 toC ..
MC74HC74 ,Dual D Flip-Flop with Set and ResetMAXIMUM RATINGS*Symbol Parameter Value UnitThis device contains protectioncircuitry to guard agains ..
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MC74HC73-MC74HC73D-MC74HC73D--MC74HC73N
Dual J-K Flip-Flop with Reset
SEMICONDUCTOR TECHNICAL DATA -
High–Performance Silicon–Gate CMOSThe MC74HC73 is identical in pinout to the LS73. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Each flip flop is negative–edge clocked and has an active–low asynchro-
nous reset.
The MC74HC73 is identical in function to the HC107, but has a different
pinout. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 92 FETs or 23 Equivalent Gates
LOGIC DIAGRAMPIN 4 = VCC
PIN 11 = GND
RESET 2
CLOCK 2
RESET 1
CLOCK 1
