MC74HC595ADR2 ,Shift Register 3-StateMAXIMUM RATINGS*Symbol Parameter Value UnitThis device contains protectioncircuitry to guard agains ..
MC74HC595ADT ,8-Bit Serial-Input/Serial or Parallel-Output Shift Register with 3-State OutputsELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎGuaranteed LimitÎV– 55 toCCVÎÎÎ SymbolÎÎ ..
MC74HC595ADTR2 ,Shift Register 3-StateLOGIC DIAGRAMQ 1 16 VB CCSERIAL14 15Q 2 15 QDATA C AA QA1INPUTQ Q 3 14 AB D2QQ 4 13 OUTPUT ENABLECE ..
MC74HC595AF ,8-Bit Serial-Input/Serial or Parallel-Output Shift Register With Latched 3-State OutputsHigh–Performance Silicon–Gate CMOSMARKINGThe MC74HC595A consists of an 8–bit shift register and an ..
MC74HC595AFEL ,Shift Register 3-StateLOGIC DIAGRAMQ 1 16 VB CCSERIAL14 15Q 2 15 QDATA C AA QA1INPUTQ Q 3 14 AB D2QQ 4 13 OUTPUT ENABLECE ..
MC74HC595AFL1 ,8-Bit Serial-Input/Serial or Parallel-Output Shift Register With Latched 3-State OutputsELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitÎÎÎV V – 55 toCC CCÎSymbol S ..
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0007TR ,Low Cost MMIC Mixer, 2.1
MC74HC595A-MC74HC595AD-MC74HC595ADR2-MC74HC595ADT-MC74HC595ADTR2-MC74HC595AFEL-MC74HC595AN
Shift Register 3-State
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High–Performance Silicon–Gate CMOSThe MC74HC595A consists of an 8–bit shift register and an 8–bit
D–type latch with three–state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8–bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2.0 to 6.0 V Low Input Current: 1.0 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 328 FETs or 82 Equivalent Gates Improvements over HC595 Improved Propagation Delays 50% Lower Quiescent Power Improved Input Noise and Latchup Immunity
LOGIC DIAGRAMSERIAL
DATA
INPUT
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SQH
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
