MC74HC564N ,Octal 3-State Inverting D Flip-FlopMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC573A ,Octal 3-State NonInverting Transparent LatchMC74HC573AOctal 3-State NoninvertingTransparent LatchHigh−Performance Silicon−Gate CMOSThe MC74HC57 ..
MC74HC573ADT ,Octal 3-State NonInverting Transparent LatchMaximum ratingsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎapplied to the device are individua ..
MC74HC573ADT ,Octal 3-State NonInverting Transparent LatchMaximum ratings are those values beyond which device damage can occur.
MC74HC573ADW ,Octal 3-State NonInverting Transparent Latchhttp://onsemi.comare compatible with standard CMOS outputs; with pullup resistors,they are compatib ..
MC74HC573ADWG , Octal 3−State Noninverting Transparent Latch High−Performance Silicon−Gate CMOS
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0007TR ,Low Cost MMIC Mixer, 2.1
MC74HC564N
Octal 3-State Inverting D Flip-Flop
SEMICONDUCTOR TECHNICAL DATA- -
High–Performance Silicon–Gate CMOSThe MC74HC564 is identical in pinout to the LS564. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is identical in function to the HC534A but has the flip–flop
inputs on the opposite side of the package from the outputs to facilitate PC
board layout.
Data meeting the setup time is clocked, in inverted form, to the outputs
with the rising edge of the Clock. The Output Enable input does not affect the
states of the flip–flops, but when Output Enable is high, all device outputs are
forced to the high–impedance state. Thus, data may be stored even when
the outputs are not enabled.
The HC564 is the inverting version of the HC574A. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 282 FETs or 70.5 Equivalent Gates
LOGIC DIAGRAMDATA
INPUTS2 Q0
CLOCK
OUTPUT
ENABLE
INVERTING
OUTPUTS
PIN 20 = VCC
PIN 10 = GND