MC74HC540AFL1 ,Octal 3-State Inverting Buffer/Line Driver/Line ReceiverMAXIMUM RATINGS*ÎÎÎÎÎÎ Symbol ParameterÎÎÎÎÎ ValueÎÎÎ UnitThis device contains protectioncircuitry ..
MC74HC540AN ,Octal 3-State Inverting Buffer/Line Driver/Line ReceiverMC74HC540AOctal 3-State InvertingBuffer/Line Driver/LineReceiverHigh–Performance Silicon–Gate CMOST ..
MC74HC541A ,Octal 3-State Non Inverter Buffer/Line Driverfeaturesinputs and outputs on opposite sides of the package and two ANDed20active–low output enable ..
MC74HC541ADT ,Octal 3-State Non Inverter Buffer/Line Driver3MC74HC541ADC CHARACTERISTICS (Voltages Referenced to GND)V Guaranteed LimitCCSymbol Parameter Cond ..
MC74HC541ADTEL ,Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver2MC74HC541ADC CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitV VCC CCV VSymbol Paramet ..
MC74HC541ADW ,Octal 3-State Non-Inverting Buffer/Line Driver/Line ReceiverMAXIMUM RATINGS (Note 1)Symbol Parameter Value UnitV DC Supply Voltage 0.5 to 7.0 VCCV DC Input V ..
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0007TR ,Low Cost MMIC Mixer, 2.1
MC74HC540AFL1
Octal 3-State Inverting Buffer/Line Driver/Line Receiver
---
High–Performance Silicon–Gate CMOSThe MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3–state memory address drivers, clock
drivers, and other bus–oriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
active–low output enables.
The HC540A is similar in function to the HC541A, which has
non–inverting outputs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating V oltage Range: 2 to 6V Low Input Current: 1μA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 124 FETs or 31 Equivalent GatesY1A1Y2A2Y3A3Y4A4Y5A5Y6A6Y7A7Y8A8
OE1OE2
Output
Enables
Data
Inputs
Inverting
Outputs
PIN 20 = VCC
PIN 10 = GND
LOGIC DIAGRAM
Pinout: 20–Lead Packages (Top View)VCC
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
FUNCTION TABLE
http://
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
PDIP–20
N SUFFIX
CASE 738
ORDERING INFORMATION
