MC74HC4046AN ,Phase-Locked LoopMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC4046AN ,Phase-Locked LoopMaximum Ratings are those values beyond which damage to the device may occur.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
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MC74HC4046AN
Phase-Locked Loop
SEMICONDUCTOR TECHNICAL DATA-
High–Performance Silicon–Gate CMOSThe MC574HC4046A is similar in function to the MC14046 Metal gate
CMOS device. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC4046A phase–locked loop contains three phase comparators, a
voltage–controlled oscillator (VCO) and unity gain op–amp DEMOUT. The
comparators have two common signal inputs, COMPIN, and SIGIN. Input
SIGIN and COMPIN can be used directly coupled to large voltage signals, or
indirectly coupled (with a series capacitor to small voltage signals). The
self–bias circuit adjusts small voltage signals in the linear region of the
amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error
signal PC1OUT and maintains 90 degrees phase shift at the center
frequency between SIGIN and COMPIN signals (both at 50% duty cycle).
Phase comparator 2 (with leading–edge sensing logic) provides digital error
signals PC2OUT and PCPOUT and maintains a 0 degree phase shift
between SIGIN and COMPIN signals (duty cycle is immaterial). The linear
VCO produces an output signal VCOOUT whose frequency is determined by
the voltage of input VCOIN signal and the capacitor and resistors connected
to pins C1A, C1B, R1 and R2. The unity gain op–amp output DEMOUT with
an external resistor is used where the VCOIN signal is needed but no loading
can be tolerated. The inhibit input, when high, disables the VCO and all
op–amps to minimize standby power consumption.
Applications include FM and FSK modulation and demodulation, frequen-
cy synthesis and multiplication, frequency discrimination, tone decoding,
data synchronization and conditioning, voltage–to–frequency conversion
and motor speed control. Output Drive Capability: 10 LSTTL Loads Low Power Consumption Characteristic of CMOS Devices Operating Speeds Similar to LSTTL Wide Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 μA Maximum (except SIGIN and COMPIN) In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Low Quiescent Current: 80 μA Maximum (VCO disabled) High Noise Immunity Characteristic of CMOS Devices Diode Protection on all Inputs Chip Complexity: 279 FETs or 70 Equivalent Gates
