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MC74HC4040AFL1-MC74HC4040AFR2
12-Stage Binary Ripple Counter
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High–Performance Silicon–Gate CMOSThe MC74C4040A is identical in pinout to the standard CMOS
MC14040. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 12 master–slave flip–flops. The output of
each flip–flop feeds the next and the frequency at each output is half of
that of the preceding one. The state counter advances on the
negative–going edge of the Clock input. Reset is asynchronous and
active–high.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
HC4040A for some designs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 398 FETs or 99.5 Equivalent Gates
LOGIC DIAGRAMQ10
Clock 10
Reset
Pin 8 = GND
VCC
Q11 Q10 Q8 Q9 Reset Clock Q1
Q11
Q12
