MC74HC374A ,Octal D-Type Flip-FlopLOGIC DIAGRAMWW = Work Week23Q0PIN ASSIGNMENTD054Q1D1 OUTPUT1 20 VCCENABLE7 6D2 Q2Q0 2 19 Q789DATA ..
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MC74HC374A-MC74HC374ADTR2-MC74HC374ADW-MC74HC374ADWR2-MC74HC374AF-MC74HC374AFEL-MC74HC374AN-MC74HC374AN.
Octal D-Type Flip-Flop
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High–Performance Silicon–Gate CMOSThe MC74HC374A is identical in pinout to the LS374. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the clock. The Output Enable input does not affect the states of
the flip–flops, but when Output Enable is high, the outputs are forced
to the high–impedance state; thus, data may be stored even when the
outputs are not enabled.
The HC374A is identical in function to the HC574A which has the
input pins on the opposite side of the package from the output. This
device is similar in function to the HC534A which has inverting
outputs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2.0 to 6.0 V Low Input Current: 1.0 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 266 FETs or 66.5 Equivalent Gates
LOGIC DIAGRAMDATA
INPUTSCLOCK18OUTPUT ENABLE
PIN 20 = VCC
PIN 10 = GND
NONINVERTING
OUTPUTS
FUNCTION TABLE
http://
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
PDIP–20
N SUFFIX
CASE 738
TSSOP–20
DT SUFFIX
CASE 948E
ORDERING INFORMATION
PIN ASSIGNMENTOUTPUT
ENABLE
GND
VCC
CLOCK
