MC74HC354N ,8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs**SEMICONDUCTOR TECHNICAL DATA**"! **!* **!*"*!*#** **!* **!* J SUFFIX* * **! CERAMIC PACKAGE20C ..
MC74HC365 ,Hex 3-State Noninverting Buffer with Common EnablesELECTRICAL CHARACTERISTICS Î (Voltages Referenced to GND)ÎÎ Guaranteed LimitÎÎÎV V – 55 toÎÎÎÎÎÎC C ..
MC74HC365N ,Hex 3-State Noninverting Buffer with Common EnablesMAXIMUM RATINGS*ÎÎÎSymbol Parameter Value UnitThis device contains protectionÎÎÎÎÎÎcircuitry to gua ..
MC74HC366N ,Hex 3-State Inverting Buffer with Common EnablesMAXIMUM RATINGS*ÎÎÎSymbol Parameter Value UnitThis device contains protectionÎÎÎÎÎÎcircuitry to gua ..
MC74HC366N ,Hex 3-State Inverting Buffer with Common EnablesELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎGuaranteed LimitV VÎÎ – 55 toÎÎÎÎC CC ..
MC74HC367 ,Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit SectionsLOGIC DIAGRAMY0 3 14 A5A1 4 13 Y52 3A0 Y0Y1 5 12 A4A2 6 11 Y44 5A1 Y1Y2 7 10 A36 7GND 8 9 Y3A2 Y210 ..
MD123 , Low-saturation, Low-voltage Bi-directional Motor Driver
MD127 , Low-saturation, Low-voltage 2 Channels Bi-directional Motor Driver
MD127 , Low-saturation, Low-voltage 2 Channels Bi-directional Motor Driver
MD127 , Low-saturation, Low-voltage 2 Channels Bi-directional Motor Driver
MD127 , Low-saturation, Low-voltage 2 Channels Bi-directional Motor Driver
MD142 , Multi-Channels Motor Driver For DSC
MC74HC354N
8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs
SEMICONDUCTOR TECHNICAL DATA"! ! !
"!# ! ! -
! -
!! "!"!
High–Performance Silicon–Gate CMOSThe MC54/74HC354 is identical in pinout to the LS354. The device
inputs are compatible with Standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC354 selects one of eight latched binary Data Inputs, as deter-
mined by the Address Inputs. The information at the Data Inputs is stored
in the transparent 8–bit Data Latch when the Data–Latch Enable pin is
held high. The Address information may be stored in the transparent
Address Latch, which is enabled by the active–high Address–Enable pin.
The device outputs are placed in high–impedance states when Output
Enable 1 is high, Output Enable 2 is high, or Output Enable 3 is low.
The HC354 has a clocked Data Latch that is not transparent. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2 to 6V Low Input Current: 1μA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 326 FET s or 81.5 Equivalent Gates
LOGIC DIAGRAMDATA
INPUTS
3–STATE
DATA
OUTPUTS
DATA–LATCH
ENABLE
ADDRESS
INPUTS
ADDRESS–LATCH
ENABLE1516
OUTPUT
ENABLES
