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Partno	Mfg	Dc	Qty	Available	Descript
MC74HC273AFL1	MOT	N/a	1002	avai	Octal D Flip-Flop with Common Clock and Reset with LSTTL Compatible Inputs
MC74HC273AFR1	MOT	N/a	1000	avai	Octal D Flip-Flop with Common Clock and Reset with LSTTL Compatible Inputs

MC74HC273AFL1 ,Octal D Flip-Flop with Common Clock and Reset with LSTTL Compatible InputsELECTRICAL CHARACTERISTICS (V = 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)CC L r fÎÎÎÎÎÎ Guarant ..
MC74HC273AFR1 ,Octal D Flip-Flop with Common Clock and Reset with LSTTL Compatible InputsELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed LimitÎÎÎÎÎÎ VÎÎÎÎÎÎ – 55 toÎÎÎÎÎ ..
MC74HC273AN ,Octal D-Type Flip-FlopELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎGuaranteed LimitÎV – 55 toCCÎÎÎÎÎSymbol P ..
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MC74HC273AFL1-MC74HC273AFR1
Octal D Flip-Flop with Common Clock and Reset with LSTTL Compatible Inputs
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High–Performance Silicon–Gate CMOS
The MC74HCT273A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT273A is identical in pinout to the LS273.
This device consists of eight D flip–flops with common Clock and
Reset inputs. Each flip–flop is loaded with a low–to–high transition of
the Clock input. Reset is asynchronous and active low. Output Drive Capability: 10 LSTTL Loads TTL/NMOS Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating V oltage Range: 4.5 to 5.5 V Low Input Current: 1.0 μA In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 284 FETs or 71 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTSCLOCK18RESET
PIN 20 = VCC
PIN 10 = GND
NONINVERTING
OUTPUTS
FUNCTION TABLE
X = Don’t Care
Z = High Impedance
http://
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
PDIP–20
N SUFFIX
CASE 738
ORDERING INFORMATION
PIN ASSIGNMENT
RESET
GND
VCC
CLOCK

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