Home ›  M › M118 > MC74HC273A-MC74HC273ADTR2-MC74HC273ADW-MC74HC273ADWR2-MC74HC273AF-MC74HC273AFEL-MC74HC273AN,Octal D-Type Flip-Flop

MC74HC273A-MC74HC273ADTR2-MC74HC273ADW-MC74HC273ADWR2-MC74HC273AF Fast Delivery,Good Price
Part Number:

If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email

Partno	Mfg	Dc	Qty	Available	Descript
MC74HC273A	ON	N/a	324	avai	Octal D-Type Flip-Flop
MC74HC273ADTR2	MOT	N/a	29439	avai	Octal D-Type Flip-Flop
MC74HC273ADW	ON	N/a	1368	avai	Octal D Flip-Flop with Common Clock and Reset
MC74HC273ADWR2	MOTOROLA	N/a	1376	avai	Octal D-Type Flip-Flop
MC74HC273AF	ON	N/a	78	avai	Octal D-Type Flip-Flop
MC74HC273AFEL	ON	N/a	1523	avai	Octal D-Type Flip-Flop
MC74HC273AN	ON/MOTO	N/a	93	avai	Octal D-Type Flip-Flop

MC74HC273ADTR2 ,Octal D-Type Flip-FlopLOGIC DIAGRAM20 273ADT SUFFIXALYW1CASE 948E23Q0D0154Q1D1A = Assembly Location7 6D2 Q2WL = Wafer Lot ..
MC74HC273ADTR2G , Octal D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS
MC74HC273ADW ,Octal D Flip-Flop with Common Clock and ResetELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)L r fGuaranteed LimitÎÎV – 55 toÎ CCÎÎÎ ..
MC74HC273ADWR2 ,Octal D-Type Flip-Flopresistors, they are compatible with LSTTL outputs.This device consists of eight D flip–flops with c ..
MC74HC273ADWR2G , Octal D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS
MC74HC273AF ,Octal D-Type Flip-FlopLOGIC DIAGRAM20 273ADT SUFFIXALYW1CASE 948E23Q0D0154Q1D1A = Assembly Location7 6D2 Q2WL = Wafer Lot ..
MD015C104KAB , Two Pin DIP/DIPGuard®
MD-113-PIN ,5-1000 MHz, high performance double-balanced mixer
MD115 , VCM Driver for Mobile Phone
MD115 , VCM Driver for Mobile Phone
MD115 , VCM Driver for Mobile Phone
MD118A , 8-BIT DAC VCM Driver with I2C Interface

---

MC74HC273A-MC74HC273ADTR2-MC74HC273ADW-MC74HC273ADWR2-MC74HC273AF-MC74HC273AFEL-MC74HC273AN
Octal D-Type Flip-Flop
------High–Performance Silicon–Gate CMOS
The MC74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of eight D flip–flops with common Clock and
Reset inputs. Each flip–flop is loaded with a low–to–high transition of
the Clock input. Reset is asynchronous and active low. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating V oltage Range: 2.0 to 6.0 V Low Input Current: 1.0 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 264 FETs or 66 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTSCLOCK18RESET
PIN 20 = VCC
PIN 10 = GND
NONINVERTING
OUTPUTS
FUNCTION TABLE
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎ
http://
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
PDIP–20
N SUFFIX
CASE 738
TSSOP–20
DT SUFFIX
CASE 948E
ORDERING INFORMATION
PIN ASSIGNMENT
RESET
GND
VCC
CLOCK

TEL:86-533-2716050      FAX:86-533-2716790     ©2020 IC PHOENIX CO.,LIMITED