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MC74HC245ADMOTN/a8avaiOctal 3-State Noninverting Bus Transceiver High-Performance Silicon-Gate CMOS


MC74HC245AD ,Octal 3-State Noninverting Bus Transceiver High-Performance Silicon-Gate CMOSresistors, they are compatible with LSTTL outputs.The HC245A is a 3–state noninverting transceiver ..
MC74HC245ADT ,Octal 3-State Non-Inverting Bus/TransceiverMC74HC245AOctal 3-State NoninvertingBus TransceiverHigh–Performance Silicon–Gate CMOSThe MC74HC245A ..
MC74HC245ADTEL ,Octal 3-State NonInverting Bus TransceiverELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)L r fÎÎGuaranteed LimitÎÎÎÎÎÎV – 55 toCCS ..
MC74HC245ADTG ,Octal 3-State Noninverting Bus TransceiverELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitÎÎÎV –55 toCCÎV 25CSymbol P ..
MC74HC245ADTR2G ,Octal 3-State Noninverting Bus TransceiverLogic DiagramFUNCTION TABLEControl InputsOutputEnable DirectionOperationL L Data Transmitted from B ..
MC74HC245ADW ,Octal 3-State Noninverting Bus TransceiverMaximum Ratings are those values beyond which damage to the device may occur. Exposure to these con ..
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MC74HC245AD
Octal 3-State Noninverting Bus Transceiver High-Performance Silicon-Gate CMOS
MC74HC245A
Octal 3-State Noninverting
Bus Transceiver
High–Performance Silicon–Gate CMOS

The MC74HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pull–up
resistors, they are compatible with LSTTL outputs.
The HC245A is a 3–state noninverting transceiver that is used for
2–way asynchronous communication between data buses. The device
has an active–low Output Enable pin, which is used to place the I/O
ports into high–impedance states. The Direction control determines
whether data flows from A to B or from B to A. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 �A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Moisture Sensitivity: MSL1 for All Packages Chip Complexity: 308 FETs or 77 Equivalent Gates
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MARKING
DIAGRAMS
ORDERING INFORMATION
TSSOP–20
DT SUFFIX
CASE 948E

SO–20
DW SUFFIX
CASE 751D

PDIP–20
N SUFFIX
CASE 783
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW= Work Week
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