MC74HC195N ,4-Bit Universal Shift RegisterMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC1G00 ,Single 2-Input NAND GateMC74HC1G00Single 2-Input NAND GateThe MC74HC1G00 is a high speed CMOS 2−input NAND gatefabricated w ..
MC74HC1G00 ,Single 2-Input NAND GateMAXIMUM RATINGSSymbol Parameter Value UnitV DC Supply Voltage 0.5 to 7.0 VCCV DC Input Voltage 0 ..
MC74HC1G00DFT1 ,Single 2-Input NAND Gate3MC74HC1G00VCCt tf rINPUTOUTPUTVINPUTCCA or B 90%50%10%CGNDL*t tPLH PHL90%50%10%OUTPUT Y*Includes a ..
MC74HC1G00DFT1G ,Single 2-Input NAND GateMaximum ratings applied to the device are individual stress limitvalues (not normal operating condi ..
MC74HC1G00DFT2 ,Single 2-Input NAND GateELECTRICAL CHARACTERISTICS (Input t = t = 6.0 ns)r fT = 25C T 85C 55C T 125CA A ASymbol ..
MCT62.S ,8-Pin DIP Dual-Channel Phototransistor Output OptocouplerAPPLICATIONSANODE 1 8 EMITTER•AC Line/Digital Logic - isolate high voltage transients• Digital Logi ..
MCT62H ,Optocoupler, Phototransistor Output, Dual ChannelAbsolute Maximum Ratings Input (Emitter)Parameter Test Conditions Symbol Value UnitReverse voltage ..
MCT7805BT ,THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORSELECTRICAL CHARACTERISTICS (V = 11 V, I = 500 mA, T = T to T [Note 1], unless otherwise noted.)in O ..
MCT7805CT ,THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORSOrder this document by MCT7800/D** * ** * *These voltage regulators are monolithic integrated circ ..
MCT7806CT ,THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORSMAXIMUM RATINGS (T = +25°C, unless otherwise noted.)ARating Symbol Value UnitInput Voltage V 35 Vdc ..
MCT7808CT ,THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORSELECTRICAL CHARACTERISTICS (V = 10 V, I = 500 mA, T = T to T [Note 1], unless otherwise noted.)in O ..
MC74HC195N
4-Bit Universal Shift Register
SEMICONDUCTOR TECHNICAL DATA -
High–Performance Silicon–Gate CMOSThe MC74HC195 is identical in pinout to the LS195. The device inputs are
compatible with standard CMOS outputs, with pull up resistors, they are
compatible with LSTTL outputs.
This static shift register features parallel load, serial load (shift right), hold,
and reset modes of operation. These modes are tabulated in the Function
Table, and further explanation can be found in the Pin Description section. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 150 FETs or 37.5 Equivalent Gates
LOGIC DIAGRAMPIN 16 = VCC
PIN 8 = GND
CLOCK
PARALLEL LOAD
RESET
SERIAL DATA
INPUTS
PARALLEL
DATA
INPUTS
PARALLEL
DATA
OUTPUTS
FUNCTION TABLEH = high level (steady state) QA0 = the level of QA before the indicated steady–state
L = low level (steady state) input conditions were established.
X = don’t care QAn, QBn, QCn = the level of QA, QB, or QC, = transition from low to high level. respectively, before the most recent transition
a, b, c, d = the level of steady–state input at inputs of the clock.
A, B, C, or D, respectively.
