MC74HC175ADR2 ,Quad D-type Flip-Flop with Common Clock and ResetMAXIMUM RATINGS*ÎÎÎÎÎÎ Symbol ParameterÎÎÎÎÎ ValueÎÎÎ UnitThis device contains protectioncircuitry ..
MC74HC175AFEL ,Quad D-type Flip-Flop with Common Clock and ResetELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)L r fÎÎGuaranteed LimitÎÎÎÎÎÎV– 55 toCCVS ..
MC74HC175AFL1 ,Quad D Flip-Flop with Common Clock and ResetELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)L r fÎÎGuaranteed LimitÎÎÎÎÎÎV– 55 toCCVS ..
MC74HC175AN ,Quad D Flip-Flop with Common Clock and Resetresistors, they are compatible with LSTTL outputs.This device consists of four D flip–flops with co ..
MC74HC175AN ,Quad D Flip-Flop with Common Clock and Reset
MC74HC175AN ,Quad D Flip-Flop with Common Clock and Reset
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MC74HC175A-MC74HC175ADR2-MC74HC175AFEL-MC74HC175AN
Quad D-type Flip-Flop with Common Clock and Reset
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High–Performance Silicon–Gate CMOSThe MC74HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of four D flip–flops with common Reset and
Clock inputs, and separate D inputs. Reset (active–low) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive going edge of the Clock input. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity 166 FETs or 41.5 Equivalent Gates
LOGIC DIAGRAMPIN 16 = VCC
PIN 8 = GND
CLOCK
RESET
DATA
INPUTS
INVERTING
AND
NONINVERTING
OUTPUTS
FUNCTION TABLE
