MC74HC174ADR2 ,Hex D-Type Flip-Flop with Clockhttp://onsemi.com3MC74HC174ADC
MC74HC174ADR2G , Hex D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS
MC74HC174ADTR2 ,Hex D-Type Flip-Flop with ClockELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)L r fV Guaranteed LimitCCSymbol Paramet ..
MC74HC174AF ,Hex D Flip-Flop with Common Clock and ResetMAXIMUM RATINGS*Symbol Parameter Value UnitThis device contains protectioncircuitry to guard agains ..
MC74HC174AFEL ,Hex D Flip-Flop with Common Clock and ResetMaximum Ratings are those values beyond which damage to the device may occur.Functional operation s ..
MC74HC174AFL1 ,Hex D Flip-Flop with Common Clock and Resetresistors, they are compatible with LSTTL outputs.This device consists of six D flip–flops with com ..
MCT277 ,Optocoupler, Phototransistor Output, With Base ConnectionElectrical CharacteristicsT = 25 °C, unless otherwise specifiedambMinimum and maximum values are te ..
MCT277 ,Optocoupler, Phototransistor Output, With Base Connection Document Number 837244 Rev. 1.4, 19-Apr-04NCTR - Normlized CTR V - Forward Voltage - VFNCTR - Norm ..
MCT277 ,Optocoupler, Phototransistor Output, With Base ConnectionMCT270/ 1/ 2/ 3/ 4/ 5/ 6/ 7VISHAYVishay SemiconductorsOptocoupler, Phototransistor Output, With Bas ..
MCT277 ,Optocoupler, Phototransistor Output, With Base ConnectionFeatures • Interfaces with common logic families Input-output coupling capacitance < 0.5 pF6A 1 B ..
MCT277 ,Optocoupler, Phototransistor Output, With Base ConnectionAbsolute Maximum RatingsT = 25 °C, unless otherwise specifiedambStresses in excess of the
MCT2E ,PHOTOTRANSISTOR OPTOCOUPLERSPHOTOTRANSISTOR OPTOCOUPLERSMCT2 MCT2E MCT210 MCT271MCT2200 MCT2201 MCT2202WHITE PACKAGE (-M SUFFIX ..
MC74HC174A-MC74HC174ADR2-MC74HC174ADTR2-MC74HC174AN
Hex D-Type Flip-Flop with Clock
MC74HC174A
Hex D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOSThe MC74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pull–up
resistors, they are compatible with LSTTL outputs.
This device consists of six D flip–flops with common Clock and
Reset inputs. Each flip–flop is loaded with a low–to–high transition of
the Clock input. Reset is asynchronous and active–low. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1.0 �A In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 162 FETs or 40.5 Equivalent Gates
Figure 1. Pin AssignmentVCC
CLOCK
RESET
GND
FUNCTION TABLE
