MC74HC173N ,Quad 3-State D Flip-Flop with Common Clock and ResetMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC174A ,Hex D-Type Flip-Flop with ClockLogic DiagramDESIGN/VALUE TABLEDesign Criteria Value UnitsÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInternal Gate Count* 40 ..
MC74HC174ADG , Hex D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS
MC74HC174ADR2 ,Hex D-Type Flip-Flop with Clockhttp://onsemi.com3MC74HC174ADC
MC74HC174ADR2G , Hex D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS
MC74HC174ADTR2 ,Hex D-Type Flip-Flop with ClockELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)L r fV Guaranteed LimitCCSymbol Paramet ..
MCT275 ,3 V, 60 mA phototransistor optocouplerRev. 1.4, 19-Apr-04 3MCT270/ 1/ 2/ 3/ 4/ 5/ 6/ 7VISHAYVishay SemiconductorsSwitching Characteristic ..
MCT276 ,3 V, 60 mA phototransistor optocouplerabsolute Maximum Ratings can cause permanent damage to the device. Functional operation of the devi ..
MCT277 ,Optocoupler, Phototransistor Output, With Base ConnectionElectrical CharacteristicsT = 25 °C, unless otherwise specifiedambMinimum and maximum values are te ..
MCT277 ,Optocoupler, Phototransistor Output, With Base Connection Document Number 837244 Rev. 1.4, 19-Apr-04NCTR - Normlized CTR V - Forward Voltage - VFNCTR - Norm ..
MCT277 ,Optocoupler, Phototransistor Output, With Base ConnectionMCT270/ 1/ 2/ 3/ 4/ 5/ 6/ 7VISHAYVishay SemiconductorsOptocoupler, Phototransistor Output, With Bas ..
MCT277 ,Optocoupler, Phototransistor Output, With Base ConnectionFeatures • Interfaces with common logic families Input-output coupling capacitance < 0.5 pF6A 1 B ..
MC74HC173N
4-bit D-type Register (with 3-state Outputs)
SEMICONDUCTOR TECHNICAL DATA "
High–Performance Silicon–Gate CMOSThe MC74HC173 is identical in pinout to the LS173. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Data, when enabled, are clocked into the four D flip–flops with the rising
edge of the common Clock. When either or both of the Output Enable
Controls is high, the outputs are in a high–impedance state. This feature
allows the HC173 to be used in bus–oriented systems. The Reset feature is
asynchronous and active high. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity 208 FETs or 52 Equivalent Gates
FUNCTION TABLE
LOGIC DIAGRAMVCC = PIN 16
GND = PIN 8
DATA
INPUTS
3–STATE
NONINVERTING
OUTPUTS
CLOCK7
DATA–
ENABLES
OUTPUT
ENABLES
DE1
DE2
OE1
OE2
RESET
