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MC74HC165N
8-Bit Serial or Parallel-Input/Serial-Output Shift Register
SEMICONDUCTOR TECHNICAL DATA #"
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High–Performance Silicon–Gate CMOSThe MC54/74HC165 is identical in pinout to the LS165. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is an 8–bit shift register with complementary outputs from the
last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load input is low, the data is loaded
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function T able).
The 2–input NOR clock may be used either by combining two independent
clock sources or by designating one of the clock inputs to act as a clock
inhibit. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 286 FETs or 71.5 Equivalent Gates
FUNCTION TABLE
LOGIC DIAGRAMPIN 16 = VCC
PIN 8 = GND
PARALLEL
DATA
INPUTS
SERIAL
DATA
INPUT
SERIAL SHIFT/PARALLEL LOAD
CLOCK
CLOCK INHIBIT
SERIAL
DATA
OUTPUTS
