MC74HC164AF ,8-Bit Serial-Input/Parallel-Output Shift RegisterMAXIMUM RATINGS*ÎÎÎÎÎÎ Symbol ParameterÎÎÎÎÎ ValueÎÎÎ UnitThis device contains protectioncircuitry ..
MC74HC164AFEL ,Shift 8-Bit Serial Input/OutputELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎGuaranteed LimitÎ−55C toVCCÎ25ÎÎ CÎÎ Sy ..
MC74HC164AFL1 ,8-Bit Serial-Input/Parallel-Output Shift RegisterELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitÎÎÎÎÎÎ V VÎÎÎÎÎÎ –55* C toÎÎ ..
MC74HC164AFR1 ,8-Bit Serial-Input/Parallel-Output Shift RegisterThe MC74HC164A is identical in pinout to the LS164. The deviceinputs are compatible with standard C ..
MC74HC164AFR1 ,8-Bit Serial-Input/Parallel-Output Shift Register3MC74HC164ATIMING REQUIREMENTS (Input t = t = 6 ns)r fÎÎÎÎÎÎ Guaranteed LimitÎÎÎÎ VÎÎÎÎÎÎ –55* C to ..
MC74HC164AN ,8-Bit Serial-Input/Parallel-Output Shift Registerresistors, they are compatible with LSTTL outputs.MARKINGThe MC74HC164A is an 8−bit, serial−input t ..
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MC74HC164ADT-MC74HC164AF-MC74HC164AFL1-MC74HC164AFR1
8-Bit Serial-Input/Parallel-Output Shift Register
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High–Performance Silicon–Gate CMOSThe MC74HC164A is identical in pinout to the LS164. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The MC74HC164A is an 8–bit, serial–input to parallel–output shift
register. Two serial data inputs, A1 and A2, are provided so that one
input may be used as a data enable. Data is entered on each rising edge
of the clock. The active–low asynchronous Reset overrides the Clock
and Serial Data inputs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAMPIN 14 = VCC
PIN 7 = GND QA
PARALLEL
DATA
OUTPUTSRESET
CLOCK8
SERIAL
DATA
INPUTS
FUNCTION TABLED = data input
QAn – QGn = data shifted from the preceding
stage on a rising edge at the clock input.