MC74HC138AD ,1-of-8 Decoder/Demultiplexer* High–Performance Silicon–Gate CMOSThe MC74HC138A is identical in pinout to the LS138. The devicei ..
MC74HC138ADR2 ,1-of-8 Decoder/DemultiplexerELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)L r fÎÎGuaranteed LimitÎÎÎÎÎÎV–55* C to ..
MC74HC138ADR2G , 1−of−8 Decoder/ Demultiplexer
MC74HC138ADR2G , 1−of−8 Decoder/ Demultiplexer
MC74HC138ADTEL ,1-of-8 Decoder/DemultiplexerLOGIC DIAGRAMA = Assembly Location115A0 Y0WL = Wafer LotADDRESS 142Y1 YY = YearA1INPUTS13WW = Work ..
MC74HC138ADTEL ,1-of-8 Decoder/DemultiplexerMAXIMUM RATINGS*Symbol Parameter Value UnitThis device contains protectioncircuitry to guard agains ..
MCR68-2 ,Silicon Controlled RectifiersMAXIMUM RATINGS (T = 25°C unless otherwise noted)JRating Symbol Value Unit(1)Peak Repetitive Off–St ..
MCR68-2 ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted.)CCharacteristic Symbol Min Typ Max Uni ..
MCR69-2 ,Silicon Controlled RectifiersMaximum ratings applied to the device are individual stress limit values (notORDERING INFORMATIONno ..
MCR69-2 ,Silicon Controlled RectifiersMAXIMUM RATINGS (T = 25°C unless otherwise noted)JRating Symbol Value UnitMARKINGPeak Repetitive Of ..
MCR69-3 ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted.)CCharacteristic Symbol Min Typ Max Uni ..
MCR703A ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)CCharacteristic Symbol Min Typ Max Unit ..
MC74HC138A-MC74HC138AD-MC74HC138ADR2-MC74HC138ADTR2-MC74HC138AF-MC74HC138AFEL-MC74HC138AN
1-of-8 Decoder/Demultiplexer
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High–Performance Silicon–Gate CMOSThe MC74HC138A is identical in pinout to the LS138. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC138A decodes a three–bit Address to one–of–eight
active–low outputs. This device features three Chip Select inputs, two
active–low and one active–high to facilitate the demultiplexing,
cascading, and chip–selecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating V oltage Range: 2.0 to 6.0 V Low Input Current: 1.0 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 100 FETs or 29 Equivalent Gates
LOGIC DIAGRAM Y6
CS1
CS2 ACTIVE–LOW
OUTPUTS
ADDRESS
INPUTS
CS3
CHIP–
SELECT
INPUTS 5
PIN 16 = VCC
PIN 8 = GND
FUNCTION TABLE
