MC74HC137N ,1-of-8 Decoder/Demultiplexer with Address LatchELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC137N ,1-of-8 Decoder/Demultiplexer with Address LatchMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC138A ,1-of-8 Decoder/DemultiplexerLOGIC DIAGRAMA = Assembly Location115A0 Y0WL = Wafer LotADDRESS 142Y1 YY = YearA1INPUTS13WW = Work ..
MC74HC138AD ,1-of-8 Decoder/Demultiplexer* High–Performance Silicon–Gate CMOSThe MC74HC138A is identical in pinout to the LS138. The devicei ..
MC74HC138ADR2 ,1-of-8 Decoder/DemultiplexerELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)L r fÎÎGuaranteed LimitÎÎÎÎÎÎV–55* C to ..
MC74HC138ADR2G , 1−of−8 Decoder/ Demultiplexer
MCR68-2 ,Silicon Controlled RectifiersMAXIMUM RATINGS (T = 25°C unless otherwise noted)JRating Symbol Value Unit(1)Peak Repetitive Off–St ..
MCR68-2 ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted.)CCharacteristic Symbol Min Typ Max Uni ..
MCR69-2 ,Silicon Controlled RectifiersMaximum ratings applied to the device are individual stress limit values (notORDERING INFORMATIONno ..
MCR69-2 ,Silicon Controlled RectifiersMAXIMUM RATINGS (T = 25°C unless otherwise noted)JRating Symbol Value UnitMARKINGPeak Repetitive Of ..
MCR69-3 ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted.)CCharacteristic Symbol Min Typ Max Uni ..
MCR703A ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)CCharacteristic Symbol Min Typ Max Unit ..
MC74HC137N
1-of-8 Decoder/Demultiplexer with Address Latch
SEMICONDUCTOR TECHNICAL DATA " -
High–Performance Silicon–Gate CMOSThe MC74HC137 is identical in pinout to the LS137. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC137 decodes a three–bit Address to one–of–eight active–low
outputs. The device has a transparent latch for storage of the Address. Two
Chip Selects, one active–low and one active–high, are provided to facilitate
the demultiplexing, cascading, and chip–selecting functions.
The demultiplexing function is accomplished by using the Address inputs
to select the desired device output, and then by using one of the Chip
Selects as a data input while holding the other one active.
The HC137 is the inverting version of the HC237. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 152 FETs or 38 Equivalent Gates
LOGIC DIAGRAMCS1
CS2
LATCH ENABLE
ADDRESS
INPUTS
PIN 16 = VCC
PIN 8 = GND
CHIP–
SELECT
INPUTS
ACTIVE–
LOW
OUTPUTS
FUNCTION TABLE = Depends upon the Address previously applied while LE was
at a low level.
