MC74HC126AN ,Quad 3-State Non-Inverting BufferMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC132 ,Quad 2-Input NAND Gate with Schmitt-Trigger Inputs
MC74HC132A ,Quad 2 Input NAND Gate with Schmitt TriggerMAXIMUM RATINGSSymbol Parameter Value UnitV Positive DC Supply Voltage 0.5 to 7.0 VCCV Digital In ..
MC74HC132A ,Quad 2 Input NAND Gate with Schmitt TriggerFeaturesPDIP−14MC74HC132ANN SUFFIX• Output Drive Capability: 10 LSTTL Loads AWLYYWWCASE 646• Output ..
MC74HC132AD ,Quad 2 Input NAND Gate with Schmitt TriggerMaximum ratings are those values beyond which device damage can occur.
MC74HC132ADR2 ,Quad 2 Input NAND Gate with Schmitt TriggerMC74HC132AQuad 2-Input NAND Gatewith Schmitt-Trigger InputsHigh−Performance Silicon−Gate CMOSThe MC ..
MCR68-2 ,Silicon Controlled RectifiersMAXIMUM RATINGS (T = 25°C unless otherwise noted)JRating Symbol Value Unit(1)Peak Repetitive Off–St ..
MCR68-2 ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted.)CCharacteristic Symbol Min Typ Max Uni ..
MCR69-2 ,Silicon Controlled RectifiersMaximum ratings applied to the device are individual stress limit values (notORDERING INFORMATIONno ..
MCR69-2 ,Silicon Controlled RectifiersMAXIMUM RATINGS (T = 25°C unless otherwise noted)JRating Symbol Value UnitMARKINGPeak Repetitive Of ..
MCR69-3 ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted.)CCharacteristic Symbol Min Typ Max Uni ..
MCR703A ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)CCharacteristic Symbol Min Typ Max Unit ..
MC74HC126AN
Quad 3-state noninverting buffers
SEMICONDUCTOR TECHNICAL DATA " !
High–Performance Silicon–Gate CMOSThe MC74HC125A and MC74HC126A are identical in pinout to the LS125
and LS126. The device inputs are compatible with standard CMOS outputs;
with pullup resistors, they are compatible with LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be used
with 3–state memory address drivers, clock drivers, and other bus–oriented
systems. The devices have four separate output enables that are active–low
(HC125A) or active–high (HC126A). Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
HC125A
Active–Low Output Enables
HC126A
Active–High Output EnablesA1
OE1
OE2
OE3
OE4
PIN 14 = VCC
PIN 7 = GND
OE1
OE2
OE3
OE4
